MPC7450EC datasheet(19/52 Pages) MOTOROLA

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MOTOROLA

MPC7450 RISC Microprocessor Hardware Speciﬁcations

Electrical and Thermal Characteristics

1.5.2.3

L3 Clock AC Speciﬁcations

The L3_CLK frequency is programmed by the L3 conﬁguration register (L3CR[6:8]) core-to-L3 divisor

ratio. See Table 17 for example core and L3 frequencies at various divisors. Table 10 provides the potential

range of L3_CLK output AC timing speciﬁcations as deﬁned in Figure 7.

The maximum L3_CLK frequency is the core frequency divided by two. However, very few SRAM designs

will be able to operate in this mode and most designs will select a greater core-to-L3 divisor to provide a

longer L3_CLK period for read and write access to the L3 SRAMs. Therefore, the maximum L3_CLK

frequency shown in Table 10 is considered to be the practical maximum in a typical system. The maximum

L3_CLK frequency for any application of the MPC7450 will be a function of the AC timings of the

MPC7450, the AC timings for the SRAM, bus loading, and printed circuit board trace length.

Motorola is similarly limited by system constraints and cannot perform tests of the L3 interface on a

socketed part on a functional tester at the maximum frequencies of Table 10. Therefore, functional operation

and AC timing information are tested at core-to-L3 divisors which result in L3 frequencies at 200 MHz or

less.

Notes:

1. The maximum L3 clock frequency will be system dependent. See Section 1.5.2.3, “L3 Clock AC Speciﬁcations” for

an explanation that this maximum frequency is not functionally tested at speed by Motorola.

2. The nominal duty cycle of the L3 output clocks is 50% measured at midpoint voltage.

3. Maximum possible skew between L3_CLK0 and L3_CLK1. This parameter is critical to the address and control

signals which are common to both SRAM chips in the L3.

4. Maximum possible skew between L3_CLK0 and L3_ECHO_CLK1 or between L3_CLK1 and L3_ECHO_CLK3 for

PB2 or Late Write SRAM. This parameter is critical to the write data signals which are separately latched onto each

SRAM part by these pairs of signals.

5. Guaranteed by design and not tested. The input jitter on SYSCLK affects L3 output clocks and the L3 address/data/

control signals equally and, therefore, is already comprehended in the AC timing and does not have to be

considered in the L3 timing analysis. The clock-to-clock jitter shown here is uncertainty in the internal clock period

caused by supply voltage noise or thermal effects. This must be accounted for, along with clock skew, in any L3

timing analysis.

Table 10. L3_CLK Output AC Timing Speciﬁcations

At recommended operating conditions. See Table 4.

Parameter

Symbol

All Speed Grades

Unit

Notes

Min

Max

L3 clock frequency

fL3_CLK

266

MHz

L3 clock cycle time

tL3_CLK

3.75

13.3

L3 clock duty cycle

tCHCL/tL3_CLK

L3 clock output-to-output skew (L1_CLK0 to L1_CLK1)

tL3CSKW1

—

200

L3 clock output-to-output skew (L1_CLK[0:1] to

L1_ECHO_CLK[1:3])

tL3CSKW2

—

100

L3 clock jitter

—

±50

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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