LPC5410X datasheet(27/95 Pages) NXP

27 / 95 page

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

27 of 95

NXP Semiconductors

LPC5410x

32-bit ARM Cortex-M4/M0+ microcontroller

• Multiprocessor/multidrop (9-bit) mode with software address compare.

• RS-485 transceiver output enable.

• Autobaud mode for automatic baud rate detection

• Parity generation and checking: odd, even, or none.

• Software selectable oversampling from 5 to 16 clocks in asynchronous mode.

• One transmit and one receive data buffer.

• RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

• FIFO support from the System FIFO.

• Received data and status can optionally be read from a single register

• Break generation and detection.

• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

• Built-in Baud Rate Generator with auto-baud function.

• A fractional rate divider is shared among all USARTs.

• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

• Loopback mode for testing of data and flow control.

• In synchronous slave mode, wakes up the part from deep sleep and power down

modes.

• Special operating mode allows operation at up to 9600 baud using the 32 kHz RTC

oscillator as the UART clock. This mode can be used while the device is in deep sleep

or power down mode and can wake-up the device when a character is received.

• USART transmit and receive functions work with the system DMA controller.

• Activity on the USART synchronous slave mode allows wake-up from deep sleep and

power down modes on any enabled interrupt.

7.16.2 SPI serial I/O controller

7.16.2.1 Features

• Master and slave operation.

• Maximum supported bit rate for SPI master mode is 48 Mbit/s, and the maximum

supported bit rate for SPI slave mode is 21 Mbit/s.

• Data frames of 1 to 16 bits supported directly. Larger frames supported by software or

DMA set-up.

• Data can be transmitted to a slave without the need to read incoming data. This can

be useful while setting up an SPI memory.

• Control information can optionally be written along with data. This allows very

versatile operation, including “any length” frames.

• Up to four Slave Select input/outputs with selectable polarity and flexible usage.

• Supports DMA transfers: SPIn transmit and receive functions can operated with the

system DMA controller.

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