LPC5410X datasheet(30/95 Pages) NXP

30 / 95 page

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

30 of 95

NXP Semiconductors

LPC5410x

32-bit ARM Cortex-M4/M0+ microcontroller

7.18.2.1 Features

• Two 16-bit counters or one 32-bit counter.

• Counter(s) clocked by bus clock or selected input.

• Up counter(s) or up-down counter(s).

• State variable allows sequencing across multiple counter cycles.

• Event combines input or output condition and/or counter match in a specified state.

• Events control outputs, interrupts, and the SCT states.

– Match register 0 can be used as an automatic limit.

– In bi-directional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• Selected event(s) can limit, halt, start, or stop a counter.

• Supports:

– 8 inputs (6 GPIO pins, ADC0_THCMP_IRQ, DEBUG_HALTED)

– up to 8 outputs

– 13 match/capture registers

– 13 events

– 13 states

• PWM capabilities including dead time and emergency abort functions

7.18.3 Windowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.

7.18.3.1 Features

• Internally resets chip if not reloaded during the programmable time-out period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time-out period, both programmable.

• Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

• Programmable 24-bit timer with internal fixed pre-scaler.

• Selectable time period from 1,024 watchdog clocks (TWDCLK  256  4) to over 67

million watchdog clocks (TWDCLK  224  4) in increments of 4 watchdog clocks.

• “Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog

reset to be disabled.

• Incorrect feed sequence causes immediate watchdog event if enabled.

• The watchdog reload value can optionally be protected such that it can only be

changed after the “warning interrupt” time is reached.

• Flag to indicate Watchdog reset.

• The Watchdog clock (WDCLK) source is the fixed 500 kHz clock (+/- 40%) provided

by the low-power watchdog oscillator.

• The Watchdog timer can be configured to run in deep sleep or power down mode.

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