LPC5410X datasheet(60/95 Pages) NXP

60 / 95 page

LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

60 of 95

NXP Semiconductors

LPC5410x

32-bit ARM Cortex-M4/M0+ microcontroller

11.5 System PLL

[1]

Data based on characterization results, not tested in production.

[2]

PLL set-up requires high-speed start-up and transition to normal mode. Lock times are only valid when

high-speed start-up settings are applied followed by normal mode settings. The procedure for setting up the

PLL is described in the LPC5410x user manual.

[3]

PLL current measured using lowest CCO frequency to obtain the desired output frequency.

Table 21.

PLL lock times and current

Tamb = 40 C to +105 C, unless otherwise specified. VDD = 1.62 V to 3.6 V

Symbol

Parameter

Conditions

Min

Typ Max

Unit

PLL configuration: input frequency 12 MHz; output frequency 75 MHz

tlock(PLL)

PLL lock time

PLL set-up procedure followed [2]

400

s

IDD(PLL)

PLL current

when locked

[1][3]

550

A

PLL configuration: input frequency 12 MHz; output frequency 100 MHz

tlock(PLL)

PLL lock time

PLL set-up procedure followed [2]

400

s

IDD(PLL)

PLL current

when locked

[1][3]

750

A

PLL configuration: input frequency 32.768 kHz; output frequency 75 MHz

tlock(PLL)

PLL lock time

[1]

6250

s

IDD(PLL)

PLL current

when locked

[1][3]

450

A

PLL configuration: input frequency 32.768 kHz; output frequency 100 MHz

tlock(PLL)

PLL lock time

[1]

6250

s

IDD(PLL)

PLL current

when locked

[1][3]

560

A

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