LPC5410X datasheet(35/95 Pages) NXP

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LPC5410x

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Product data sheet

Rev. 2.11 — 19 September 2019

35 of 95

NXP Semiconductors

LPC5410x

32-bit ARM Cortex-M4/M0+ microcontroller

7.20.4.1 Sleep mode

When sleep mode is entered, the clock to the core is stopped along with any unused

peripherals. Waking up from the sleep mode does not need any special sequence other

than re-enabling the clock to the ARM core.

In sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during sleep mode and may generate

interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic

power used by the processor itself, memory systems and related controllers, internal

buses, and unused peripherals. The processor state and registers, peripheral registers,

and internal SRAM values are maintained, and the logic levels of the pins remain static.

7.20.4.2 Deep sleep mode

In deep sleep mode, all peripheral clocks and all clock sources are off with the option of

keeping the 32 kHz clock and the WDOSC running. In addition, all analog blocks are shut

down and the flash is put in stand-by mode. In deep sleep mode, the application can keep

some of the internal clocks and the BOD circuit running for self-timed wake-up and BOD

protection.

The LPC5410x can wake up from deep sleep mode via a reset, digital pins selected as

inputs to the pin interrupt block, RTC alarm, Micro-tick, a watchdog timer reset interrupt,

BOD interrupt/reset, or an interrupt from the USART (in 32 kHz mode or synchronous

slave mode), the SPI, or any of the I2C peripherals. For wake-up from deep sleep mode,

the SPI, USART, and I2C peripherals must be configured in slave mode.

Any interrupt used for waking up from deep sleep mode must be enabled in one of the

SYSCON wake-up enable registers and the NVIC.

In deep sleep mode, the processor state and registers, peripheral registers, and internal

SRAM values are maintained, and the logic levels of the pins remain static. deep sleep

mode allows for very low quiescent power and fast wake-up options.

7.20.4.3 Power down mode

In power down mode, all peripheral clocks and all clock sources are off with the option of

keeping the 32 kHz clock, and the WDOSC running. In addition, all analog blocks and the

flash are shut down. In power down mode, the application can keep the BOD circuit

running for BOD protection.

The LPC5410x can wake up from power down mode via a reset, digital pins selected as

inputs to the pin interrupt block, RTC alarm, Micro-tick, a watchdog timer reset interrupt,

BOD interrupt/reset, or an interrupt from the USART (in 32 kHz mode or synchronous

slave mode), the SPI, or any of the I2C peripherals. For wake-up from power down mode,

the SPI, USART, and I2C peripherals must be configured in slave mode.

In power down mode, the processor state and registers, peripheral registers, and internal

SRAM values are maintained, and the logic levels of the pins remain static. Power down

mode reduces power consumption compared to deep sleep mode at the expense of

longer wake-up times.

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