MPF5024AMMA0ES datasheet(20/93 Pages) NXP

20 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

20 / 93

aaa-030046

LP_OFF State

tpwrup_lpm

Self-Test

RESETBMCU

Regulator Outputs

Fuse load OK

(internal signal)

STEST done

(internal signal)

PWRON

V1P5D

UVDET

VIN

Fuse

Load

tfuseLoad

1.6 V

tvin_rise

treg2reset

tfirst

Figure 7. Startup with PWRON driven high externally and bit LPM_OFF = 0

Table 16. Startup with PWRON driven high externally and LPM_OFF = 0

Symbol

Parameter

Min

Typ

Max

Unit

tvin_rise

Rise time of VIN from VPWR application to UVDET

(system dependent)

—

1500

µs

tfuseload

Time from VIN crossing UVDET to Fuse_Load_done

(fuse loaded correctly)

—

600

µs

tpwrup_lpm

Time from PWRON going high to the first slot of the

power up sequence

—

800

µs

14.5 Power up

14.5.1 Power up events

Upon a power cycle (VIN > UVDET), the LPM_OFF bit is reset to 0, therefore the device

moves to the LP_Off state by default. The actual value of the LPM_OFF bit can be

changed during the Run mode and is maintained until VIN crosses the UVDET threshold.

In either one of the Off modes, the PF5024 can be enabled by the following power up

events:

1. When OTP_PWRON_MODE = 0, PWRON pin is pulled high.

2. When OTP_PWRON_MODE = 1, PWRON pin experiences a high to low transition

and remains low for as long as the PWRON_DBNC timer.

A power up event is valid only if:

• VIN > UVDET

• VIN < VIN_OVLO (unless the OVLO is disabled or OTP_VIN_OVLO_SDWN = 0)

MPF5024AMMA0ES Datasheet(PDF) 20 Page - NXP Semiconductors

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