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MPF5024AMMA0ES Datasheet(PDF) 8 Page - NXP Semiconductors |
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MPF5024AMMA0ES Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 93 page  NXP Semiconductors PF5024 Power management integrated circuit (PMIC) for high performance applications PF5024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved. Product data sheet Rev. 1 — 15 April 2020 8 / 93 12.3 Power tree summary The following table provides a summary of the voltage regulators in the PF5024. Table 8. Voltage supply summary Regulator Type Input supply Regulated output range (V) VOUT programmable step (mV) IRATED (mA) SW1 Buck SW1IN 0.4 V to 1.8 V 6.25 2500 SW2 Buck SW2IN VTT/0.4 V to 1.8 V 6.25 2500 SW3 Buck SW3IN 0.4 V to 1.8 V 6.25 2500 SW4 Buck SW4IN 0.4 V to 1.8 V 6.25 2500 12.4 Device differences Table 9. Device differences Description PF5024 non-safety PF5024 ASIL B Bits not available on PF5024 non- safety During the self-test, the device checks: • The high speed oscillator circuit is operating within a maximum of 15 % tolerance • A CRC is performed on the mirror registers during the self-test routine to ensure the integrity of the registers before powering up • The output of both the voltage generation bandgap and the monitoring bandgap are not more than 5 % to 12 % apart from each other • ABIST test on all voltage monitors and toggling signals Not available Available AB_SWx_OV AB_SWx_UV STEST_NOK AB_RUN Fail-safe state: to lock down the system in case of critical failures cycling the PMIC ON/OFF. Not available Available FS_CNT[3:0] OTP_FS_BYPASS OTP_FS_MAX_CNT[3:0] OTP_FS_OK_TIMER[2:0] Secure I2C write: I2C write procedure to modify registers dedicated to safety features (I2C CRC is still available). Not available Available I2C_SECURE_EN OTP_I2C_SECURE _EN (always 0) RANDOM_GEN[7:0] RANDOM_CHK[7:0] |
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