MPF5024AMMA0ES datasheet(91/93 Pages) NXP

91 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 15 April 2020

91 / 93

Tables

Tab. 1.

Ordering information ..........................................2

Tab. 2.

Pin description ...................................................4

Tab. 3.

Absolute maximum ratings ................................5

Tab. 4.

ESD ratings .......................................................5

Tab. 5.

Thermal characteristics ..................................... 6

Tab. 6.

QFN40 thermal resistance and package

dissipation ratings ............................................. 6

Tab. 7.

Operating conditions ......................................... 6

Tab. 8.

Voltage supply summary ...................................8

Tab. 9.

Device differences .............................................8

Tab. 10. State machine transition definition .................. 10

Tab. 11. Fail-safe OK timer configuration ......................17

Tab. 12. UVDET threshold ............................................ 17

Tab. 13. VIN_OVLO debounce configuration ................ 18

Tab. 14. VIN_OVLO specifications ................................18

Tab. 15. Startup timing requirements (PWRON pulled

up) ................................................................... 19

Tab. 16. Startup with PWRON driven high externally

and LPM_OFF = 0 .......................................... 20

Tab. 17. Power up time base register ........................... 21

Tab. 18. Power up sequence registers ..........................21

Tab. 19. Power down regulator group bits .................... 25

Tab. 20. Power down counter delay ..............................25

Tab. 21. Programmable delay after RESETBMCU is

asserted ...........................................................25

Tab. 22. Power down delay selection ............................26

Tab. 23. Regulator control during fault event bits ..........27

Tab. 24. Fault timer register configuration .....................30

Tab. 25. Fault bypass bits .............................................30

Tab. 26. Interrupt registers ............................................ 35

Tab. 27. I/O electrical specifications ..............................36

Tab. 28. PWRON debounce configuration in edge

detection mode ................................................38

Tab. 29. TRESET configuration .....................................38

Tab. 30. Standby pin polarity control .............................38

Tab. 31. PGOODx assignment ......................................41

Tab. 32. ENx assignment .............................................. 41

Tab. 33. I2C address configuration ............................... 45

Tab. 34. Secure bits ...................................................... 46

Tab. 35. Internal supplies electrical characteristics ....... 47

Tab. 36. SWx ramp rates .............................................. 48

Tab. 37. SWx output voltage configuration ....................49

Tab. 38. SWx regulator mode configuration .................. 49

Tab. 39. SWx current limit selection ..............................50

Tab. 40. SWx phase configuration ................................ 50

Tab. 41. SWx inductor selection bits .............................50

Tab. 42. OTP_SW1CONFIG register description .......... 51

Tab. 43. OTP_SW4CONFIG register description .......... 51

Tab. 44. Type

buck

regulator

electrical

characteristics ..................................................52

Tab. 45. Recommended external components ..............54

Tab. 46. UV threshold configuration register ................. 54

Tab. 47. OV threshold configuration register .................55

Tab. 48. UV debounce timer configuration ....................55

Tab. 49. OV debounce timer configuration ....................55

Tab. 50. VMON electrical characteristics ...................... 57

Tab. 51. Manual frequency tuning configuration ............59

Tab. 52. Clock management specifications ...................61

Tab. 53. Thermal monitor specifications ........................63

Tab. 54. Thermal monitor bit description .......................63

Tab. 55. AMUX channel selection ................................. 64

Tab. 56. Watchdog duration register ............................. 65

Tab. 57. Soft WD register reset .....................................67

Tab. 58. Default hardwire configuration .........................79

Tab. 59. Quiescent current requirements ...................... 82

Tab. 60. Revision history ...............................................88

Figures

Fig. 1.

Simplified application diagram ...........................2

Fig. 2.

Internal block diagram .......................................3

Fig. 3.

Pin configuration for 40-pin QFN .......................4

Fig. 4.

Functional block diagram .................................. 7

Fig. 5.

State diagram ....................................................9

Fig. 6.

Startup with PWRON pulled up .......................19

Fig. 7.

Startup with PWRON driven high externally

and bit LPM_OFF = 0 ..................................... 20

Fig. 8.

Power up/down sequence between Off and

system On state ..............................................22

Fig. 9.

Power up/down sequence between run and

standby ............................................................23

Fig. 10.

Group power down sequence example ...........26

Fig. 11.

Power down delay ...........................................27

Fig. 12.

Regulator turned off upon with RegX_

STATE = 0 and FLT_REN = 0 ........................ 28

Fig. 13.

Regulator turned off upon with RegX_

STATE = 0 and FLT_REN = 1 ........................ 29

Fig. 14.

Correct power up (no fault during power up) ....32

Fig. 15.

Power up sequencer with a temporary failure .. 33

Fig. 16.

Power up sequencer aborted as fault

persists for longer than 2.0 ms ........................34

Fig. 17.

I/O interface diagram .......................................36

Fig. 18.

XFAILB behavior during a power up

sequence .........................................................43

Fig. 19.

XFAILB behavior during a power down

sequence .........................................................43

Fig. 20.

Behavior during an external XFAILB event ......44

Fig. 21.

External XFAILB event during a power up

sequence .........................................................44

Fig. 22.

8 bit SAE J1850 CRC polynomial ................... 46

Fig. 23.

Buck regulator block diagram ..........................48

Fig. 24.

Voltage monitoring architecture .......................56

Fig. 25.

Clock management architecture ......................58

Fig. 26.

Spread-spectrum waveforms ...........................60

Fig. 27.

Thermal monitoring architecture ......................62

Fig. 28.

Watchdog timer operation ............................... 66

Fig. 29.

Soft WD reset behavior ...................................68

MPF5024AMMA0ES Datasheet(PDF) 91 Page - NXP Semiconductors

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