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STM32H723VG Datasheet(PDF) 112 Page - STMicroelectronics |
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STM32H723VG Datasheet(HTML) 112 Page - STMicroelectronics |
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112 / 227 page ![]() Electrical characteristics STM32H723xE/G 112/227 DS13313 Rev 2 6.3.11 PLL characteristics The parameters given in Table 38, Table 41 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 12: General operating conditions. Table 38. PLL1 characteristics (wide VCO frequency range)(1) Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock - 2 - 16 MHz PLL input clock duty cycle - 10 - 90 % fPLL_P_OUT PLL multiplier output clock P VOS0 1.5 - 550(2) MHz VOS1 1.5 - 400(2) VOS2 1.5 - 300(2) VOS3 1.5 - 170(2) fVCO_OUT PLL VCO output - 192 - 836(3) tLOCK PLL lock time Normal mode 15 50 150(3) µs Sigma-delta mode (CKIN ≥ 8 MHz) 25 65 170 Jitter Cycle-to-cycle jitter(4) fPLL_OUT = fVCO_OUT/100 fVCO_OUT = 192 MHz -51 - ps fVCO_OUT = 400 MHz -19 - fVCO_OUT = 560 MHz -10 - fVCO_OUT = 800 MHz -9 - Period jitter fVCO_OUT = 192 MHz -38 - fVCO_OUT = 560 MHz -8 - fVCO_OUT = 800 MHz -7 - Long term jitter Normal mode (CKIN = 2 MHz) fVCO_OUT = 192 MHz -0.15 - fVCO_OUT = 400 MHz -0.14 - fVCO_OUT = 832 MHz -0.16 - Sigma-delta mode (CKIN = 16 MHz) fVCO_OUT = 192 MHz -0.17 - fVCO_OUT = 500 MHz -0.08 - fVCO_OUT = 836 MHz -0.06 - |
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