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STM32H723VG Datasheet(PDF) 113 Page - STMicroelectronics |
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STM32H723VG Datasheet(HTML) 113 Page - STMicroelectronics |
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113 / 227 page  DS13313 Rev 2 113/227 STM32H723xE/G Electrical characteristics 208 IDD(PLL) PLL power consumption fVCO_OUT = 560 MHz VDDA 530 557 670 µA VCORE 1190 1285 6300 fVCO_OUT = 192 MHz VDDA 260 286 513 VCORE 309 377 5700 1. Guaranteed by design unless otherwise specified. 2. This value must be limited to the maximum frequency due to the product limitation. 3. Guaranteed by characterization results. 4. Integer mode only. Table 38. PLL1 characteristics (wide VCO frequency range)(1) (continued) Symbol Parameter Conditions Min Typ Max Unit Table 39. PLL1 characteristics (medium VCO frequency range)(1) Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock - 1 - 2 MHz PLL input clock duty cycle - 10 - 90 % fPLL_OUT PLL multiplier output clock P, Q, R VOS0 1.17 - 210 MHz VOS1 1.17 - 210 VOS2 1.17 - 210 VOS3 1.17 - 200 fVCO_OUT PLL VCO output - 150 - 420 tLOCK PLL lock time Normal mode - 60(2) 100(2) µs Sigma-delta mode forbidden Jitter Cycle-to-cycle jitter(3) - fVCO_OUT = 150 MHz -145 - ±ps fVCO_OUT = 300 MHz -91 - fVCO_OUT = 400 MHz -64 - fVCO_OUT = 420 MHz -63 - Period jitter fPLL_OUT = 50 MHz fVCO_OUT = 150 MHz -55 - ±-ps fVCO_OUT = 400 MHz -30 - Long term jitter Normal mode fVCO_OUT = 400 MHz -±0.3 - % I(PLL) PLL power consumption on VDD fVCO_OUT = 420 MHz VDD - 440 1150 µA VCORE - 530 - fVCO_OUT = 150 MHz VDD - 180 500 VCORE - 200 - |
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