ACE25QC200GLTMTH datasheet(19/64 Pages) ACE

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ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

Configuration and Status Instructions

Write Enable (06H)

The Write Enable instruction (Figure 2.) sets the Write Enable Latch (WEL) bit in the Status Register to a 1.

The WEL bit must be set prior to every Page Program, Dual Page Program, Quad Page Program, Page

Erase, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security

Registers instruction. The Write Enable instruction is entered by driving

/CS low, shifting the instruction code “06h” into the Data Input (SI) pin on the rising edge of SCLK, and then

driving /CS high.

Write Enable for Volatile Status Register (50h)

The non-volatile Status Register bits described in Status Register can also be written to as volatile bits. This

gives more flexibility to change the system configuration and memory protection schemes quickly without

waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register

non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile

Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write

Enable for Volatile Status Register instruction (Figure 3. will not set the Write Enable Latch (WEL) bit, it is

only valid for the Write Status Register instruction to change the volatile Status Register bit values.

Figure2. Write Enable Instruction for SPI Mode

Figure3. Write Enable for Volatile Status Register Instruction for SPI Mode

ACE25QC200GLTMTH Datasheet(PDF) 19 Page - ACE Technology Co., LTD.