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ACE25QC200GLTMTH Datasheet(PDF) 42 Page - ACE Technology Co., LTD.

Part # ACE25QC200GLTMTH
Description  2M BIT SPI NOR FLASH
PDF  64 Pages
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Manufacturer  ACE [ACE Technology Co., LTD.]
Direct Link  http://www.ace-ele.com
Logo ACE - ACE Technology Co., LTD.

ACE25QC200GLTMTH Datasheet(HTML) 42 Page - ACE Technology Co., LTD.

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ACE25QC200GL
2M BIT SPI NOR FLASH
VER 1.1
42
Program/Erase Suspend (75h)
The Program/Erase Suspend instruction “75h”, allows the system to interrupt a Page Program or a
Page/Sector/32K/64K Block Erase operation and then read data from any other sector or block. After the
program or erase operation has entered the suspended state, the memory array can be read except for the
page being programmed or the sector or block being erased. And after the erase operation has entered the
suspended state, the memory array can be programed except for the page being erased. Write status
register operation can't be suspended. Erase/Program security registers operation can't be suspended.
The Program/Erase Suspend instruction sequence is shown in Figure33.
Readable Area of Memory While a Program or Erase Operation is Suspended
Suspended operation
Readable Region Of Memory Array
Page Program
All but the Page being programmed
Dual Page Program
All but the Page being programmed
Quad Page Program
All but the Page being programmed
Page Erase
All but the Page being Erased
Sector Erase(4KB)
All but the 4KB Sector being Erased
Block Erase(32KB)
All but the 32KB Block being Erased
Block Erase(64KB)
All but the 64KB Block being Erased
When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL before the
Write Enable Latch (WEL) bit clears to “0” and the SUS2 or SUS1 sets to “1”, after which the device is
ready to accept one of the commands listed in "Table Acceptable Commands During Program/Erase
Suspend after tPSL/tESL" (e.g. FAST READ). Refer to " AC Characteristics" for tPSL and tESL timings.
"Table Acceptable instructions During Suspend (tPSL/tESL not required)" lists the Instructions for which the
tPSL and tESL latencies do not apply. For example, “05h”, “48h”, “66h” and “99h” can be issued at any time
after the Suspend instruction.
Status Register bit 15 (SUS2) and bit 10 (SUS1) can be read to check the suspend status. The SUS2
(Program Suspend Bit) sets to “1” when a program instruction is suspended. The SUS1 (Erase Suspend Bit)
sets to “1” when an erase operation is suspended. The SUS2 or SUS1 clears to “0” when the program or
erase instruction is resumed.



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