ACE25QC200GLTMTH datasheet(47/64 Pages) ACE

47 / 64 page

ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

Read Security Registers (48h)

The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data

bytes to be sequentially read from one of the three security registers. The instruction is initiated by driving

the /CS pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight

“dummy” clocks into the SI pin. The code and address bits are latched on the rising edge of the SCLK pin.

After the address is received, the data byte of the addressed memory location will be shifted out on the SO

pin at the falling edge of SCLK with most significant bit (MSB) first. The byte address is automatically

incremented to the next byte address after each byte of data is shifted out. Once the byte address reaches

the last byte of the register (byte address FFh), it will reset to address 00h, the first byte of the register, and

continue to increment. The instruction is completed by driving /CS high. The Read Security Register

instruction sequence is shown in Figure37. If a Read Security Register instruction is issued while an Erase,

Program or Write cycle is in progress (WIP=1) the instruction is ignored and will not have any effects on the

current cycle. The Read Security Register instruction allows clock frequency up to to a maximum of fC (see

AC Electrical Characteristics).

Address

A23-16

A15-12

A11-9

A8-A0

Security Registers 1

00H

0001

0000

Byte Address

Security Registers 2

00H

0010

0000

Byte Address

Security Registers 3

00H

0011

0000

Byte Address

Figure37. Read Security Registers instruction

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