ACE25QC200GLTMTH datasheet(34/64 Pages) ACE

34 / 64 page

ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

Read JEDEC ID (9Fh)

The Read JEDEC ID instruction can operate at the highest possible frequency of fC (see AC Electrical

Characteristics). For compatibility reasons, the ACE25QC200GL provides several instructions to

electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the

JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated

by driving the /CS pin low and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID

byte for (68h) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted

out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure23. For memory type

and capacity values refer to Manufacturer and Device Identification table.

Read Unique ID Number (4Bh)

The Read Unique ID Number instruction can operate at the highest possible frequency of fC (see AC

Electrical Characteristics).The Read Unique ID Number instruction accesses a factory-set read-only

128-bit number that is unique to each ACE25QC200GL device. The ID number can be used in conjunction

with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction

is initiated by driving the /CS pin low and shifting the instruction code “4Bh” followed by a four bytes of

dummy clocks. After which, the 128-bit ID is shifted out on the falling edge of SCLK as shown in Figure24.

Figure23. Read JEDEC ID Instruction

Figure24. Read Unique ID Sequence Diagram

ACE25QC200GLTMTH Datasheet(PDF) 34 Page - ACE Technology Co., LTD.