ST25DV04KC datasheet(75/203 Pages) STMICROELECTRONICS

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The output data comes from consecutive addresses, with the internal address counter automatically incremented

after each byte output.

Sequential read in user memory:

•

Sequential read can cross area borders. Device continue to output data bytes until the internal address

counter is reaching a non readable address (either address that don't exist or if read protected with I2C

security session closed).

•

When internal address counter reach a non readable address, device releases the SDA line and continues

to output FFh.

•

There is no roll over at the end of user memory. When internal address counter reaches end of user

memory, device continue to output bytes located in Dynamic registers area, until it reaches a non readable

address.

Sequential read in system memory:

•

There is no roll over after reaching end of system memory (ST25DVxxKC returns only FFh after last system

memory byte address).

Sequential read in dynamic registers:

•

It is possible to read sequentially dynamic register and fast transfer mode’s mailbox (contiguous I2C

addresses). There is no roll over at the end of dynamic registers area.

Sequential read in mailbox:

•

There is no roll over at the end of the mailbox (ST25DVxxKC returns only FFh after last mailbox memory

byte address).

6.5.4

Acknowledge in read mode

For all Read commands, the device waits, after each byte read, for an acknowledgement during the ninth bit time.

If the bus master does not drive serial data (SDA) low during this time, the device terminates the data transfer and

switches to its Standby mode.

6.6

I²C password management

The controls I²C security session using an I²C 64-bit password. This I²C password is managed with two I²C

dedicated commands: I²C present password and I²C write password.

6.6.1

I2C present password command description

The I2C present password command is used in I2C mode to present the password to the ST25DVxxKC. This is

used to open I2C security session or to allow I2C password modification (see Section 5.6 Data protection for

detailed explanation about password usage).

Following a Start condition, the bus master sends a device select code with the Read/ Write bit (R W ) reset to 0

and the Chip Enable bit E2 at 1 and E1 at 1. The device acknowledges this, as shown in Figure 36. I2C Present

Password Sequence, and waits for two I2C password address bytes, 09h and 00h. The device responds to each

address byte with an acknowledge bit, and then waits for the eight password data bytes, the validation code, 09h,

and a resend of the eight password data bytes. The most significant byte of the password is sent first, followed by

the least significant bytes.

It is necessary to send the 64-bit password twice to prevent any data corruption during the sequence. If the two

64-bit passwords sent are not exactly the same, the ST25DVxxKC does not start the internal comparison.

When the bus master generates a Stop condition, immediately after the Ack bit (during the tenth bit time slot), the

ST25DVxxKC compares the 64 received data bits with the 64 bits of the stored I2C password. If the values match,

the I2C security session is open, and the I2C_SSO_Dyn register is set to 01h. If the values do not match, the I2C

security session is closed and I2C_SSO_dyn register is set to 00h.

I2C_SSO_Dyn is a Dynamic register, it can be checked via I2C host to know If I2C security session is open.

ST25DV04KC ST25DV16KC ST25DV64KC

I²C password management

DS13519 - Rev 3

page 75/203

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