ST25DV04KC datasheet(41/203 Pages) STMICROELECTRONICS

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5.4.2

ST25DVxxKC interrupt capabilities on I2C events

On top of RF events, the ST25DVxxKC provides two additional I2C events that can trigger an interrupt on the

GPO pin.

In this section, all drawings are referring to the open drain version of GPO output (8-pin packages).

The reader can retrieve the behaviour of CMOS version (12-pin package) by inverting the GPO curve polarity and

replace the word “released” or “high-Z” by “pull to ground”.

Supported I2C events is listed hereafter:

I2C_WRITE:

•

When I2C_WRITE is activated, a pulse of duration IT_TIME is emitted at completion of a valid I2C write

operation in EEPROM (after I2C STOP condition).

•

Note that writing in dynamic registers or fast transfer mode mailbox does not trigger I2C_WRITE interrupt

(no write operation in EEPROM).

•

The purpose of this GPO interrupt is to inform the I2C host when the I2C write programming cycle in

EEPROM is completed, meaning the I2C bus and RF interface are free for new operation.

Figure 24. GPO/I2C_WRITE chronogram

1) I2C host sends a valid write command to EEPROM. ST25DVxxKC program the data into EEPROM.

GPO/I2C_WRITE generates a pulse during IT_TIME after programming cycle completion.

m * Wt

GPO/I2C_WRITE

3) I2C host sends a valid write command to Dynamic register or Mailbox. ST25DVxxKC program the

data with no programming cycle. GPO/I2C_WRITE remains high-Z.

2) I2C host sends an invalid write command to EEPROM. ST25DVxxKC does not program the data

into EEPROM. GPO/I2C_WRITE remains High-Z.

GPO/I2C_WRITE

S I2C Write A P

S I2C Write N P

S I2C Write A P

GPO/I2C_WRITE

MS69215

ST25DV04KC ST25DV16KC ST25DV64KC

GPO

DS13519 - Rev 3

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