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MPC5675KFF0VMS2R Datasheet(PDF) 101 Page - NXP Semiconductors |
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MPC5675KFF0VMS2R Datasheet(HTML) 101 Page - NXP Semiconductors |
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101 / 147 page  Electrical characteristics MPC5675K Microcontroller Data Sheet, Rev. 9 NXP Semiconductors 101 3.21.2 Reset sequence description The figures in this section show the internal states of the MPC5675K during the five different reset sequences. The doted lines in the figures indicate the starting point and the end point for which the duration is specified in Table 58. The start point and end point conditions as well as the reset trigger mapping to the different reset sequences is specified in Section 3.21.3, Reset sequence trigger mapping. With the beginning of DRUN mode, the first instruction is fetched and executed. At this point, application execution starts and the internal reset sequence is finished. The following figures show the internal states of the MPC5675K during the execution of the reset sequence and the possible states of the RESET signal pin. NOTE RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an external reset generator or by the MPC5675K internal reset circuitry. A high level on this pin can only be generated by an external pullup resistor which is strong enough to overdrive the weak internal pulldown resistor. The rising edge on RESET in the following figures indicates the time when the device stops driving it low. The reset sequence durations given in Table 58 are applicable only if the internal reset sequence is not prolonged by an external reset generator keeping RESET asserted low beyond the last PHASE3. Figure 12. Destructive reset sequence, BIST enabled Table 58. RESET sequences No. Symbol Parameter TReset Unit Min Typ Max1 1 The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET by an external reset generator. 1 TDRB CC Destructive Reset Sequence, BIST enabled 50 60 70 ms 2 TDR CC Destructive Reset Sequence, BIST disabled 40 400 1000 µs 3 TERLB CC External Reset Sequence Long, BIST enabled 50 60 70 ms 4 TFRL CC Functional Reset Sequence Long 40 300 600 µs 5 TFRS CC Functional Reset Sequence Short 1 3 10 µs PHASE0 PHASE1,2 PHASE3 PHASE1,2 PHASE3 DRUN BIST Reset Sequence Trigger Reset Sequence Start Condition RESET Establish Flash Device Self MBIST LBIST Application IRC and PWR Init Test Setup Config Flash Init Device Config Execution TDRB, min < TRESET < TDRB, max |
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