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MPC5675KFF0VMS2R Datasheet(PDF) 102 Page - NXP Semiconductors |
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MPC5675KFF0VMS2R Datasheet(HTML) 102 Page - NXP Semiconductors |
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102 / 147 page  MPC5675K Microcontroller Data Sheet, Rev. 9 Electrical characteristics NXP Semiconductors 102 Figure 13. Destructive reset sequence, BIST disabled Figure 14. External reset sequence long, BIST enabled Figure 15. Functional reset sequence long PHASE0 PHASE1,2 PHASE3 DRUN Reset Sequence Trigger Reset Sequence Start Condition RESET Establish Flash Device Application IRC and PWR Init Config Execution TDR, min < TRESET < TDR, max PHASE1,2 PHASE3 PHASE1,2 PHASE3 DRUN BIST Reset Sequence Trigger Reset Sequence Start Condition RESET Flash Device Self MBIST LBIST Application Init Test Setup Config Flash Init Device Config Execution TERLB, min < TRESET < TERLB, max PHASE1,2 PHASE3 DRUN Reset Sequence Trigger Reset Sequence Start Condition RESET Application Flash Init Device Config Execution TFRL, min < TRESET < TFRL, max |
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