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MPC5675KFF0VMS2R Datasheet(PDF) 103 Page - NXP Semiconductors |
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MPC5675KFF0VMS2R Datasheet(HTML) 103 Page - NXP Semiconductors |
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103 / 147 page ![]() Electrical characteristics MPC5675K Microcontroller Data Sheet, Rev. 9 NXP Semiconductors 103 Figure 16. Functional reset sequence short The reset sequences shown in Figure 15 and Figure 16 are triggered by functional reset events. RESET is driven low during these two reset sequences only if the corresponding functional reset source (which triggered the reset sequence) was enabled to drive RESET low for the duration of the internal reset sequence. See the RGM_FBRE register in the MPC5675K Reference Manual for more information. 3.21.3 Reset sequence trigger mapping The following table shows the possible trigger events for the different reset sequences, depending on the VREG mode (external or internal). It specifies the reset sequence start conditions as well as the reset sequence end indications that are the basis for the timing data provided in Table 58. PHASE3 DRUN Reset Sequence Trigger Reset Sequence Start Condition RESET Application Execution TFRS, min < TRESET < TFRS, max |
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