NAND01G-B2C datasheet(31/67 Pages) NUMONYX

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NAND01G-B2C

Device operations

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6.6

Reset

The Reset command is used to reset the command interface and status register. If the

Reset command is issued during any operation, the operation will be aborted. If it was a

program or erase operation that was aborted, the contents of the memory locations being

modified will no longer be valid as the data will be partially programmed or erased.

If the device has already been reset then the new Reset command will not be accepted.

The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value

of tBLBH4 depends on the operation that the device was performing when the command was

issued, refer to Table 25: AC characteristics for operations for the values.

6.7

Read status register

The device contains a status register which provides information on the current or previous

program or erase operation. The various bits in the status register convey information and

errors on the operation.

The status register is read by issuing the Read Status Register command. The status

Enable or Read Enable, whichever occurs last. When several memories are connected in a

system, the use of Chip Enable and Read Enable signals allows the system to poll each

device separately, even when the Ready/Busy pins are common-wired. It is not necessary to

toggle the Chip Enable or Read Enable signals to update the contents of the status register.

After the Read Status Register command has been issued, the device remains in read

status register mode until another command is issued. Therefore if a Read Status Register

command is issued during a random read cycle a new Read command must be issued to

continue with a page read operation.

The Status Register bits are summarized in Table 11: Status register bits,. Refer to Table 11

in conjunction with the following text descriptions.

6.7.1

Write protection bit (SR7)

The write protection bit can be used to identify if the device is protected or not. If the write

protection bit is set to ‘1’ the device is not protected and program or erase operations are

allowed. If the write protection bit is set to ‘0’ the device is protected and program or erase

operations are not allowed.

6.7.2

P/E/R controller and cache ready/busy bit (SR6)

Status register bit SR6 has two different functions depending on the current operation.

During cache read operations SR6 indicates whether the next selected page can be read

from the page register (SR6 is set to '1') or not (SR6 is set to '0').

During all other operations SR6 acts as a P/E/R controller bit, which indicates whether the

P/E/R controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R

controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive

(device is ready).

NAND01G-B2C Datasheet(PDF) 31 Page - Numonyx B.V

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