NAND01G-B2C datasheet(38/67 Pages) NUMONYX

38 / 67 page

Device operations

NAND01G-B2C

38/67

80-83

Number of data bytes per page

84-85

Number of spare bytes per page

86-89

Number of data bytes per partial page

90-91

Number of spare bytes per partial page

92-95

Number of pages per block

96-99

Number of blocks per logical unit (LUN)

100

Number of logical units (LUNs)

101

Number of address cycles

Bit 4 to bit 7

Column address cycles

Bit 0 to bit 3

Row address cycles

102

Number of bits per cell

103-104

Bad blocks maximum per LUN

105-106

Block endurance

107

Guaranteed valid blocks at beginning of

target

108-109

Block endurance for guaranteed valid

blocks

110

Number of programs per page

111

Partial programming attributes

Bit 5 to bit 7

Reserved

1 = partial page layout is partial page

data followed by partial page spare

Bit 1 to bit 3

Reserved

1 = partial page programming has

constraints

112

Number of bits ECC correctability

113

Number of interleaved address bits

Bit 4 to bit 7

Reserved (0)

Bit 0 to bit 3

Number of interleaved address bits

114

Interleaved operation attributes

Bit 4 to bit 7

Reserved (0)

Bit 3

Address restrictions for program cache

Bit 2

1 = program cache supported

Bit 1

1 = no block address restrictions

Bit 0

Overlapped / concurrent interleaving

support

115-127

Reserved (0)

Table 16.

Parameter page data structure (continued)

Byte

O/M(1)

Description

NAND01G-B2C Datasheet(PDF) 38 Page - Numonyx B.V

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