NRF9160-SICA-R7 datasheet(16/400 Pages) NORDIC

16 / 400 page

Product overview

Peripheral

core

TASK n

write

task

event

EVENT m

IRQ signal to NVIC

INTEN

Peripheral

SHORTS

Channel outputs to DPPI

SUBSCRIBE n

PUBLISH m

Channel inputs from DPPI

CHIDX

Figure 2: Peripheral interface

The distributed programmable peripheral interconnect (DPPI) feature enables peripherals to connect

events to tasks without CPU intervention.

Note: For more information on DPPI and the DPPI channels, see DPPI - Distributed programmable

peripheral interconnect on page 86.

3.3.1 Peripheral ID

Every peripheral is assigned a fixed block of 0x1000 bytes of address space, which is equal to 1024 x 32 bit

registers.

See Instantiation on page 24 for more information about which peripherals are available and where

they are located in the address map.

There is a direct relationship between peripheral ID and base address. For example, a peripheral with base

address 0x40000000 is assigned ID=0, a peripheral with base address 0x40001000 is assigned ID=1, and a

peripheral with base address 0x4001F000 is assigned ID=31.

Peripherals may share the same ID, which may impose one or more of the following limitations:

• Shared registers or common resources

• Limited availability due to mutually exclusive operation; only one peripheral in use at a time

4418_1315 v2.0

NRF9160-SICA-R7 Datasheet(PDF) 16 Page - Nordic Semiconductor