NRF9160-SICA-R7 datasheet(98/400 Pages) NORDIC

98 / 400 page

Peripherals

• Trigger interrupt on state changes on any pin

• All pins can be used by the PPI task/event system

• One or more GPIO outputs can be controlled through PPI and GPIOTE channels

• All pins can be individually mapped to interface blocks for layout flexibility

• GPIO state changes captured on SENSE signal can be stored by LATCH register

• Support for secure and non-secure attributes for pins in conjunction with the system protection unit

(SPU — System protection unit on page 259)

GPIO port and the GPIO pin details on page 98 illustrates the GPIO port containing 32 individual pins,

where

PIN0 is illustrated in more detail as a reference. All signals on the left side in the illustration are

used by other peripherals in the system and therefore not directly available to the CPU.

GPIO Port

PIN31

PIN0

PIN31

PIN[31].CNF

PIN[31].IN

PIN[31].OUT

PIN0

PIN[0].CNF

PIN[0].IN

PIN[0].OUT

PIN0

PIN[0].OUT

PIN[0].IN

Sense

OUT_OVERRIDE

DIR_OVERRIDE

PIN0.DETECT

OUT

O: output buffer

I: input buffer

PIN[0].CNF.INPUT

PIN[0].CNF.PULL

PIN[0].CNF.DRIVE

PIN[0].CNF.SENSE

PIN[0].CNF.DIR

INPUT_OVERRIDE

ANAIN

ANAEN

PIN1.DETECT

PIN31.DETECT

LATCH

LDETECT

DETECT

DETECTMODE

Figure 17: GPIO port and the GPIO pin details

6.4.1 Pin configuration

The GPIO port peripheral implements up to 32 pins,

PIN0 through PIN31. Each of these pins can be

individually configured in the PIN_CNF[n] registers (n=0..31).

The following parameters can be configured through these registers:

• Direction

• Drive strength

• Enabling of pull-up and pull-down resistors

• Pin sensing

• Input buffer disconnect

• Analog input (for selected pins)

Note: All write-capable registers are retained registers, see POWER — Power control on page 64

for more information.

The input buffer of a GPIO pin can be disconnected from the pin to enable power savings when the pin is

not used as an input, see GPIO port and the GPIO pin details on page 98. Inputs must be connected to

get a valid input value in the IN register, and for the sense mechanism to get access to the pin.

Other peripherals in the system can connect to GPIO pins and override their output value and

configuration, or read their analog or digital input value. See GPIO port and the GPIO pin details on page

98.

Selected pins also support analog input signals, see ANAIN in GPIO port and the GPIO pin details on page

98. The assignment of the analog pins can be found in Pin assignments on page 385.

The following delays should be taken into considerations:

• There is a delay of 2 CPU clock cycles from the GPIO pad to the IN register.

4418_1315 v2.0

NRF9160-SICA-R7 Datasheet(PDF) 98 Page - Nordic Semiconductor

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