NRF9160-SICA-R7 datasheet(101/400 Pages) NORDIC

101 / 400 page

Peripherals

page 101 illustrates how the DETECT_NSEC and DETECT_SEC signals are generated from the GPIO

PIN[].DETECT signals.

SPU.GPIOPORT[].PERM register

PIN[0].DETECT

PIN[n].DETECT

PIN[31].DETECT

LATCH

GPIO.DETECTMODE_SEC

DETECT_SEC

GPIO.DETECTMODE

DETECT_NSEC

to GPIOTE

to GPIOTESEC

DETECT

Figure 19: Principle of direct pin access

6.4.4 Registers

Base address Peripheral

Instance

Secure mapping

DMA security

Description

Configuration

0x50842500

0x40842500

GPIO

P0 : S

P0 : NS

SPLIT

General purpose input and

output

Table 37: Instances

Offset

Security Description

OUT

0x004

Write GPIO port

This register is retained.

OUTSET

0x008

Set individual bits in GPIO port

OUTCLR

0x00C

Clear individual bits in GPIO port

0x010

Read GPIO port

DIR

0x014

Direction of GPIO pins

This register is retained.

DIRSET

0x018

DIR set register

DIRCLR

0x01C

DIR clear register

LATCH

0x020

Latch register indicating what GPIO pins that have met the criteria set in the

PIN_CNF[n].SENSE registers

This register is retained.

4418_1315 v2.0

101

NRF9160-SICA-R7 Datasheet(PDF) 101 Page - Nordic Semiconductor

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