NRF9160-SICA-R7 datasheet(172/400 Pages) NORDIC

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Peripherals

6.10.3 Limitations

The previous compare value is repeated if the PWM period is shorter than the time it takes for the

EasyDMA to retrieve from RAM and update the internal compare registers. This is to ensure a glitch-free

operation even for very short PWM periods.

Only SEQ[1] can trigger the LOOPSDONE event upon completion, not SEQ[0]. This requires looping to be

enabled (LOOP > 0) and SEQ[1].CNT > 0 when sequence playback starts.

6.10.4 Pin configuration

The OUT[n] (n=0..3) signals associated with each PWM channel are mapped to physical pins according to

the configuration of PSEL.OUT[n] registers. If PSEL.OUT[n].CONNECT is set to Disconnected, the associated

PWM module signal will not be connected to any physical pins.

The PSEL.OUT[n] registers and their configurations are used as long as the PWM module is enabled and

the PWM generation active (wave counter started). They are retained only as long as the device is in

System ON mode (see the POWER section for more information about power modes).

To ensure correct behavior in the PWM module, the pins that are used must be configured in the GPIO

peripheral in the following way before the PWM module is enabled:

PWM signal

PWM pin

Direction

Output value

Comment

OUT[n]

As specified in PSEL.OUT[n]

(n=0..3)

Output

Idle state defined in GPIO OUT

Table 59: Recommended GPIO configuration before starting PWM generation

The idle state of a pin is defined by the OUT register in the GPIO module, to ensure that the pins used by

the PWM module are driven correctly. If PWM generation is stopped by triggering a STOP task, the PWM

module itself is temporarily disabled or the device temporarily enters System OFF. This configuration must

be retained in the GPIO for the selected pins (I/Os) for as long as the PWM module is supposed to be

connected to an external PWM circuit.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in

unpredictable behavior.

6.10.5 Registers

Base address Peripheral

Instance

Secure mapping

DMA security

Description

Configuration

0x50021000

0x40021000

PWM

PWM0 : S

PWM0 : NS

Pulse width modulation unit 0

0x50022000

0x40022000

PWM

PWM1 : S

PWM1 : NS

Pulse width modulation unit 1

0x50023000

0x40023000

PWM

PWM2 : S

PWM2 : NS

Pulse width modulation unit 2

0x50024000

0x40024000

PWM

PWM3 : S

PWM3 : NS

Pulse width modulation unit 3

Table 60: Instances

Offset

Security Description

TASKS_STOP

0x004

Stops PWM pulse generation on all channels at the end of current PWM period, and stops

sequence playback

4418_1315 v2.0

172

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