NRF9160-SICA-R7 datasheet(282/400 Pages) NORDIC

282 / 400 page

Peripherals

In Timer mode, the TIMER's internal Counter register is incremented by one for every tick of the timer

frequency fTIMER as illustrated in Block schematic for timer/counter on page 281. The timer frequency

is derived from PCLK16M as shown in the following example, using the values specified in the PRESCALER

fTIMER = 16 MHz / (2PRESCALER)

When fTIMER ≤ 1 MHz, TIMER will use PCLK1M instead of PCLK16M for reduced power consumption.

In counter mode, the TIMER's internal Counter register is incremented by one each time the COUNT task

is triggered, meaning the timer frequency and the prescaler are not utilized in counter mode. Similarly, the

COUNT task has no effect in Timer mode.

The TIMER's maximum value is configured by changing the bit-width of the timer in register BITMODE on

page 289.

PRESCALER on page 289 and BITMODE on page 289 must only be updated when the timer is stopped.

If these registers are updated while the timer is started, unpredictable behavior may occur.

When the timer is incremented beyond its maximum value, the Counter register will overflow and the

timer will automatically start over from zero.

The Counter register can be cleared by triggering the CLEAR task. This will explicitly set the internal value

to zero.

TIMER implements multiple capture/compare registers.

Independent of prescaler setting, the accuracy of TIMER is equivalent to one tick of the timer frequency

fTIMER as illustrated in Block schematic for timer/counter on page 281.

6.16.1 Capture

TIMER implements one capture task for every available capture/compare register.

Every time the CAPTURE[n] task is triggered, the Counter value is copied to the CC[n] register.

6.16.2 Compare

TIMER implements one COMPARE event for every available capture/compare register.

A COMPARE event is generated when the Counter is incremented and then becomes equal to the

value specified in one of the capture compare registers. When the Counter value becomes equal to the

value specified in a capture compare register CC[n], the corresponding compare event COMPARE[n] is

generated.

BITMODE on page 289 specifies how many bits of the Counter register and the capture/compare

The COMPARE event can be configured to operate in one-shot mode by configuring the corresponding

ONESHOTEN[n] register. COMPARE[n] event is generated the first time the Counter matches CC[n] after

CC[n] has been written.

6.16.3 Task delays

After TIMER is started, the CLEAR, COUNT, and STOP tasks are guaranteed to take effect within one clock

cycle of the PCLK16M.

6.16.4 Task priority

4418_1315 v2.0

282

NRF9160-SICA-R7 Datasheet(PDF) 282 Page - Nordic Semiconductor