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NRF9160-SICA-R7 Datasheet(PDF) 331 Page - Nordic Semiconductor |
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NRF9160-SICA-R7 Datasheet(HTML) 331 Page - Nordic Semiconductor |
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331 / 400 page  Peripherals 6.18.10 Electrical specification 6.18.10.1 TWIS slave timing specifications Symbol Description Min. Typ. Max. Units fTWIS,SCL Bit rates for TWIS19 100 400 kbps tTWIS,START Time from PREPARERX/PREPARETX task to ready to receive/ transmit 1.5 µs tTWIS,SU_DAT Data setup time before positive edge on SCL – all modes 300 ns tTWIS,HD_DAT Data hold time after negative edge on SCL – all modes 500 ns tTWIS,HD_STA,100kbps TWI slave hold time from for START condition (SDA low to SCL low), 100 kbps 5200 ns tTWIS,HD_STA,400kbps TWI slave hold time from for START condition (SDA low to SCL low), 400 kbps 1300 ns tTWIS,SU_STO,100kbps TWI slave setup time from SCL high to STOP condition, 100 kbps 5200 ns tTWIS,SU_STO,400kbps TWI slave setup time from SCL high to STOP condition, 400 kbps 1300 ns tTWIS,BUF,100kbps TWI slave bus free time between STOP and START conditions, 100 kbps 4700 ns tTWIS,BUF,400kbps TWI slave bus free time between STOP and START conditions, 400 kbps 1300 ns SCL SDA tHD_STA tSU_DAT tHD_DAT 1/fSCL tSU_STO tBUF Figure 103: TWIS timing diagram, 1 byte transaction 6.19 UARTE — Universal asynchronous receiver/ transmitter with EasyDMA The Universal asynchronous receiver/transmitter with EasyDMA (UARTE) offers fast, full-duplex, asynchronous serial communication with built-in flow control (CTS, RTS) support in hardware at a rate up to 1 Mbps, and EasyDMA data transfer from/to RAM. Listed here are the main features for UARTE: • Full-duplex operation • Automatic hardware flow control • Optional even parity bit checking and generation • EasyDMA • Up to 1 Mbps baudrate • Return to IDLE between transactions supported (when using HW flow control) • One or two stop bit • Least significant bit (LSB) first 19 High bit rates or stronger pull-ups may require GPIOs to be set as High Drive, see GPIO chapter for more details. 4418_1315 v2.0 331 |
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