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HC705V8GRS/D Datasheet(PDF) 139 Page - NXP Semiconductors

Part # HC705V8GRS/D
Description  The Motorola MC68HC705V8 microcontroller is a custom HC05 based MCU featuring a Message Data Link Controller (MDLC) module and on-chip power regulation.
PDF  172 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

HC705V8GRS/D Datasheet(HTML) 139 Page - NXP Semiconductors

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SECTION 15: MESSAGE DATA LINK CONTROLLER
Page 128
MC68HC705V8 Specification Rev. 2.1
15.6
MDLC PHYSICAL INTERFACE
All analog functions involved in transmitting and receiving from the J1850 bus are
performed by the Physical Interface. The Physical Interface serves to buffer the incoming
messages, wave-shape the messages being transmitted, and protect the MDLC from
transients occurring on the J1850 bus.
15.6.1
OUTLINE
The receiver analog comparator and transmitter drivers are included in the MDLC Physical
Interface and together are referred to as the "transceiver".
The transceiver provides a waveshaped 7V bus waveform in response to a timed logic
signal from the MUX Interface. The transceiver actively drives the bus high, and passively
lets an RC network pull the bus low. In order to achieve the 7V level necessary for the bus
signal, the transceiver uses a battery supply (VBATT) which is nominally 12V. The
transceiver also receives bus waveforms and provides the MUX Interface with unfiltered
input data
A low power mode of operation is automatically entered if the CPU executes a STOP or
WAIT instruction.
In the event that ground is lost, the transceiver senses this condition and releases the bus
by switching the LOAD pin to a high impedance instead of a low impedance to ground.The
transceiver also protects the MDLC by not passing on any standard disruptive or non-
disruptive signals seen on the bus to the rest of the MDLC.
The Physical Interface contains its own power-on reset circuit that is used to reset its
control circuitry whenever a power-on condition is detected.
See Figure 15-16 :
MDLC Physical Interface Outline for an example mechanization for
interfacing the MDLC module to the J1850 multiplex bus physical layer. Although this
example mechanization is designed to provide some transient protection beyond what the
Physical Interface
To CPU
Protocol Handler
MUX Interface
CPU Interface
Rx/Tx
Buffers
To J1850 Bus
MDLC
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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