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HC705V8GRS/D Datasheet(PDF) 89 Page - NXP Semiconductors

Part # HC705V8GRS/D
Description  The Motorola MC68HC705V8 microcontroller is a custom HC05 based MCU featuring a Message Data Link Controller (MDLC) module and on-chip power regulation.
PDF  172 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

HC705V8GRS/D Datasheet(HTML) 89 Page - NXP Semiconductors

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SECTION 11: 16-BIT TIMER
Page 78
MC68HC705V8 Specification Rev. 2.1
NOTE:
The Input Capture pin (TCAP) and the Output Compare pin (TCMP) are
shared with PB7 and PB6 respectively. The timer’s TCAP input is always
connected to PB7. PB6 is the timer’s TCMP pin if the OCE bit in the
MISCELLANEOUS control register is set. See 7.2.2 OCE - Output
compare enable.
11.4
TIMER CONTROL REGISTER (TCR) - $12
The TCR is a read/write register containing six control bits. Three bits control interrupts
associated with the timer status register flags ICF, OCF and TOF.
Figure 11-3:
Timer Control Register - $12
11.4.1
ICIE - Input Capture Interrupt Enable
1 - Interrupt enabled
0 - Interrupt disabled
11.4.2
OCIE - Output Compare Interrupt Enable
1 - Interrupt enabled
0 - Interrupt disabled
11.4.3
TOIE - Timer Overflow Interrupt Enable
1 - Interrupt enabled
0 - Interrupt disabled
11.4.4
TON - Timer On
When disabled, the timer is initialized to the reset condition.
1 - Timer enabled
0 - Timer disabled
11.4.5
IEDG - Input Edge
Value of input edge determines which level transition on TCAP pin will trigger free-
running counter transfer to the input capture register. Reset clears this bit.
1 - Positive edge
0 - Negative edge
ICIE
OCIE
TOIE
0
0
TON
IEDG
OLVL
RESET
$12
00
0
0
0
0
00
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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