HC705V8GRSSLASHD datasheet(3/172 Pages) NXP

3 / 172 page

Page iv

MC68HC705V8 Specification Rev. 2.1

3.4.5

EEPGM - EEPROM Programming Power Enable .............. 28

3.5

OPERATION IN STOP AND WAIT .......................................... 30

SECTION 4

CPU CORE .....................................................................31

4.1

REGISTERS............................................................................. 31

4.1.1

ACCUMULATOR (A) .......................................................... 31

4.1.2

INDEX REGISTER (X) ........................................................ 31

4.1.3

STACK POINTER (SP) ....................................................... 32

4.1.4

PROGRAM COUNTER (PC) .............................................. 32

4.1.5

CONDITION CODE REGISTER (CCR) .............................. 32

SECTION 5

INTERRUPTS .................................................................35

5.1

CPU INTERRUPT PROCESSING ........................................... 35

5.2

RESET INTERRUPT SEQUENCE........................................... 38

5.3

SOFTWARE INTERRUPT (SWI) ............................................. 38

5.4

HARDWARE INTERRUPTS..................................................... 38

5.5

EXTERNAL INTERRUPT (IRQ) ............................................... 38

5.5.1

IRQ CONTROL/STATUS REGISTER (ICSR) $1F ............. 40

5.5.2

EXTERNAL INTERRUPT TIMING ...................................... 42

5.6

16-BIT TIMER INTERRUPT ..................................................... 43

5.7

MDLC INTERRUPT.................................................................. 43

5.8

SPI INTERRUPT ...................................................................... 43

5.9

8-BIT TIMER INTERRUPT ....................................................... 44

SECTION 6

RESETS..........................................................................45

6.1

EXTERNAL RESET (RESET) .................................................. 45

6.2

INTERNAL RESETS ................................................................ 46

6.2.1

POWER-ON RESET (POR)................................................ 46

6.2.2

OPERATION IN STOP AND WAIT ..................................... 46

6.2.3

COMPUTER OPERATING PROPERLY RESET (COPR) .. 48

6.2.4

LOW-VOLTAGE RESET (LVR) .......................................... 49

6.2.5

ILLEGAL ADDRESS ........................................................... 50

6.2.6

DISABLED STOP INSTRUCTION ...................................... 50

SECTION 7

POWER SUPPLY AND REGULATION .........................51

7.1

INTERNAL POWER SUPPLY .................................................. 51

7.1.1

PRIMARY 5V REGULATOR ............................................... 51

7.1.2

SECONDARY REGULATOR .............................................. 51

7.2

MISCELLANEOUS REGISTER ............................................... 52

7.2.1

IGNS - Ignition status bit ..................................................... 52

7.2.2

OCE - Output compare enable ........................................... 52

7.2.3

PDC - Power Down Control ................................................ 52

7.3

POWER MODING .................................................................... 53

7.4

REGULATOR CONTROL LOGIC ............................................ 55

7.4.1

MASK OPTIONS................................................................. 56

7.5

POWER SUPPLY CONFIGURATION...................................... 59

7.5.1

DECOUPLING RECOMMENDATIONS .............................. 59

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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