HC705V8GRSSLASHD datasheet(64/172 Pages) NXP

64 / 172 page

SECTION 7: POWER SUPPLY AND REGULATION

Page 53

MC68HC705V8 Specification Rev. 2.1

This bit has no affect unless the REGEN bit in the MOR is set. This bit is not affected by

reset and must be initialized by software.

7.3

POWER MODING

A flow diagram depicting all conditions that the MCU could enter is shown in Figure 7-2.

The chip can be operated in one of three distinct power modes. The first mode is "Power

off". In this mode, the chip is not being powered from any source. The VBATT pin voltage is

below that required by the regulator circuit to provide an output voltage that is within

regulation limits.

The second mode is "Standby power". In this mode, the VBATT voltage is above the

required minimum, but the user has not turned the primary regulator on. The secondary

regulator and the power mode logic are powered up. Standby mode can be exited by either

reducing the VBATT voltage or by turning the primary regulator on.

The third mode is "Power up" mode. In this mode the CPU and peripherals can perform

their normal processing tasks. The only way to exit from this mode is to lose regulator

output power. Losing regulator output power can happen in one of three ways: 1) the VBATT

voltage can fall below the required minimum level causing VDD to fall below minimum, 2)

software can turn the primary regulator off, and 3) some sort of fault on the external VDD

pin. In any case, the LVR reset will be asserted to protect the system as the VDD voltage is

falling.

Transitioning between these states is referred to as power moding.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705V8GRS/D Datasheet(PDF) 64 Page - NXP Semiconductors