HC705V8GRSSLASHD datasheet(2/172 Pages) NXP

2 / 172 page

Page iii

MC68HC705V8 Specification Rev. 2.1

TABLE OF CONTENTS

SECTION 1

GENERAL DESCRIPTION .............................................. 1

1.1

FEATURES.................................................................................1

1.2

MASK OPTIONS ........................................................................2

1.3

PIN ASSIGNMENTS...................................................................2

1.4

MCU STRUCTURE ....................................................................8

1.5

FUNCTIONAL PIN DESCRIPTION ............................................9

1.5.1

VBATT/VPP .............................................................................9

1.5.2

VDD AND VSS ........................................................................9

1.5.3

VSSA1.....................................................................................9

1.5.4

VSSA2.....................................................................................9

1.5.5

VCCA ......................................................................................9

1.5.6

VREFH AND VREFL.................................................................9

1.5.7

OSC1, OSC2 .......................................................................10

1.5.8

RESET ................................................................................ 11

1.5.9

IRQ (MASKABLE INTERRUPT REQUEST) .......................11

1.5.10

PA0-PA7..............................................................................11

1.5.11

PB0-PB5, PB6/TCMP, PB7/TCAP ......................................11

1.5.12

PC0-PC7 .............................................................................11

1.5.13

AD0-AD7 / PD0-PD7: AD8-AD15/PE0-PE7 ........................12

1.5.14

PWM....................................................................................12

1.5.15

PF0/SS, PF1/SCK, PF2/MOSI, PF3/MISO .........................12

1.5.16

BUS, LOAD, REXT1, REXT2 ..............................................12

1.5.17

VIGN .....................................................................................13

SECTION 2

MEMORY MAP .............................................................. 15

2.1

SINGLE-CHIP MODE MEMORY MAP .....................................15

2.2

I/O AND CONTROL REGISTERS ............................................15

2.3

RAM ..........................................................................................16

2.4

BOOTROM ...............................................................................17

2.5

EPROM.....................................................................................17

2.6

EEPROM ..................................................................................17

SECTION 3

EPROM AND EEPROM ................................................. 23

3.1

EPROM BOOTLOADER...........................................................23

3.1.1

BOOTLOADER FUNCTIONS .............................................23

3.2

EPROM PROGRAMMING........................................................23

3.2.1

PROGRAMMING REGISTER $0D .....................................24

3.3

MASK OPTION REGISTER (MOR) $3C00 ..............................25

3.4

EEPROM PROGRAMMING REGISTER $1C ..........................27

3.4.1

CPEN - Charge Pump Enable .............................................27

3.4.2

ER1:ER0 - Erase Select Bits ...............................................27

3.4.3

LATCH.................................................................................28

3.4.4

EERC - EEPROM RC Oscillator Control .............................28

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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