HC705V8GRSSLASHD datasheet(5/172 Pages) NXP

5 / 172 page

Page vi

MC68HC705V8 Specification Rev. 2.1

11.6

TIMER DURING WAIT MODE ................................................. 80

11.7

TIMER DURING STOP MODE................................................. 80

SECTION 12

CORE TIMER .................................................................81

12.1

CORE TIMER CTRL & STATUS REGISTER (CTCSR) $08.... 82

12.1.1

CTOF - Core Timer Over Flow............................................ 82

12.1.2

RTIF - Real Time Interrupt Flag .......................................... 82

12.1.3

TOFE - Timer Over Flow Enable......................................... 82

12.1.4

RTIE - Real Time Interrupt Enable...................................... 82

12.1.5

TOFC - Timer Over Flow Flag Clear ................................... 82

12.1.6

RTFC - Real Time Interrupt Flag Clear ............................... 83

12.1.7

RT1:RT0 - Real Time Interrupt Rate Select ........................ 83

12.2

COMPUTER OPERATING PROPERLY (COP) RESET .......... 83

12.3

CORE TIMER COUNTER REGISTER (CTCR) $09 ................ 84

12.4

TIMER DURING WAIT MODE ................................................. 84

SECTION 13

PULSE WIDTH MODULATOR.......................................85

13.1

FUNCTIONAL DESCRIPTION ................................................. 85

13.2

REGISTERS............................................................................. 86

13.2.1

PWM CONTROL................................................................. 87

13.2.2

PWM DATA REGISTERS ................................................... 88

13.3

PWM DURING WAIT MODE.................................................... 88

13.4

PWM DURING STOP MODE ................................................... 88

13.5

PWM DURING RESET ............................................................ 88

SECTION 14

SERIAL PERIPHERAL INTERFACE .............................89

14.1

SPI SIGNAL DESCRIPTION .................................................... 89

14.1.1

Master In Slave Out (MISO/PF3) ........................................ 90

14.1.2

Master Out Slave In (MOSI/PF2) ........................................ 90

14.1.3

Serial Clock (SCK/PF1) ...................................................... 90

14.1.4

Slave Select (SS/PF0) ........................................................ 91

14.2

FUNCTIONAL DESCRIPTION ................................................. 91

14.3

SPI REGISTERS ...................................................................... 93

14.3.1

Serial Peripheral Control Register (SPCR) ......................... 93

14.3.2

Serial Peripheral Status Register (SPSR)........................... 94

14.3.3

Serial Peripheral Data I/O Register (SPDR) ....................... 95

14.4

SPI IN STOP MODE ............................................................... 96

14.5

SPI IN WAIT MODE ................................................................. 96

SECTION 15

MESSAGE DATA LINK CONTROLLER.......................97

15.1

OUTLINE .................................................................................. 98

15.1.1

MDLC OPERATING MODES.............................................. 99

15.1.2

MODE DESCRIPTIONS ..................................................... 99

15.2

MDLC CPU INTERFACE ....................................................... 101

15.2.1

OUTLINE .......................................................................... 101

15.2.2

MDLC CONTROL REGISTER (MCR) $0E ....................... 102

15.2.3

MDLC STATUS REGISTER (MSR) $0F........................... 105

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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