HC705V8GRSSLASHD datasheet(40/172 Pages) NXP

40 / 172 page

SECTION 3: EPROM AND EEPROM

Page 29

MC68HC705V8 Specification Rev. 2.1

To erase a byte of EEPROM set LATCH = 1, CPEN = 1, ER1 = 0 and ER0 = 1, write to the

address to be erased, and set EEPGM for a time t

EBYT.

To erase a block of EEPROM set LATCH = 1, CPEN = 1, ER1 = 1 and ER0 = 0, write to

any address in the block, and set EEPGM for a time t

EBLOCK.

For a bulk erase set LATCH = 1, CPEN = 1, ER1 = 1, and ER0 = 1, write to any address

in the array, and set EEPGM for a time t

EBULK.

To terminate the programming or erase sequence, clear EEPGM, delay for a time t

FPV to

allow the programming voltage to fall, and then clear LATCH and CPEN to free up the

buses. Following each erase or programming sequence, clear all programming control bits.

The following program is an example of the EEPROM programming sequence using the

timer to implement the required delay and assuming a 2.1 MHz bus frequency.

TSR

EQU

$0013

TIMER STATUS REGISTER

TCNTH

EQU

$0018

TIMER COUNTER REGISTER (HIGH)

TCNTL

EQU

$0019

TIMER COUNTER REGISTER (LOW)

TCMPH

EQU

$0016

TIMER OUTPUT COMPARE REGISTER (HIGH)

TCMPL

EQU

$0017

TIMER OUTPUT COMPARE REGISTER (LOW)

OCF

EQU

OCF BIT OF TSR

PROG

EQU

$001C

PROGRAM REGISTER

CPEN

EQU

CHARGE PUMP ENABLE

ER1

EQU

ERASE SELECT 1

ER0

EQU

ERASE SELECT 0

LATCH

EQU

LATCH BIT

EERC

EQU

RC/OSC SELECTOR

EEPGM

EQU

EE PROGRAM BIT

EESTART EQU

$0240

STARTING ADDRESS OF EEPROM

SUMPIN

EQU

$55

DUMMY DATA

ORG

$0F00

START

EQU

BSET

EERC,PROG

SELECT RC OSC

BSR

DELAY

RC OSC STABILIZATION

BSET

CPEN,PROG

TURN ON CHARGE PUMP

BSET

LATCH,PROG

ENABLE LATCH BIT

Table 3-3:

EEPROM Write/Erase Cycle Reduction

EEPROM Data To Be

Programmed

EEPROM Data Before

Programming

Erase Before

Programming?

Yes

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705V8GRS/D Datasheet(PDF) 40 Page - NXP Semiconductors

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