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STM32U5A5QJ Datasheet(PDF) 304 Page - STMicroelectronics

Part # STM32U5A5QJ
Description  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU,240 DMIPS, 4 MB Flash, 2.5 MB SRAM, LTDC, MIPI® DSI, crypto
PDF  382 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32U5A5QJ Datasheet(HTML) 304 Page - STMicroelectronics

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Electrical characteristics
STM32U5Axxx
304/382
DS13543 Rev 1
Figure 49. PSSI transmit timing diagram
tOV(DATA)
Data output valid time
2.7 V ≤ VDD ≤ 3.6 V
-
14
ns
1.71 V ≤ VDD ≤ 3.6 V
-
21
tOH(DATA)
Data output hold time
1.71 V ≤ VDD ≤ 3.6 V
7-
tOV(DE)
DE output valid time
-
13.5
tOH(DE)
DE output hold time
6
-
tSU(RDY)
RDY input setup time
0
-
tH(RDY)
RDY input hold time
0
-
1. Evaluated by characterization. Not tested in production.
2. This maximal frequency does not consider receiver setup and hold timings.
Table 114. PSSI transmit characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Max
Unit
MSv63437V1
ts(RDY)
tho(DATA)
tv(DATA)
CKPOL=0
CKPOL=1
PSSI D[15:0]
(output)
th(RDY)
tw(PDCKL)
tw(PDCKH)
tc(PDCK)
tf(PDCK)
Invalid data OUT
Valid data OUT
DEPOL=0
DEPOL=1
RDYPOL=0
RDYPOL=1
Invalid data OUT
tr(PDCK)
tv(DE)
tho(DE)
Table 115. PSSI receive characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
-
Frequency ratio DCMI_PDCK/fHCLK
--
0.4
-
PSSI_PDCK PSSI clock input
1.71 V ≤ VDD ≤ 3.6 V
-
64
MHz
DPIXEL
PSSI clock input duty cycle
-
30
70
%



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