STM32U5A5QJ datasheet(343/382 Pages) STMICROELECTRONICS

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DS13543 Rev 1

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STM32U5Axxx

Electrical characteristics

348

5.3.42

SAI characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the ambient temperature, fPCLKx frequency and VDD supply voltage

conditions summarized inTable 33, with the following configuration:

•

Output speed set to OSPEEDRy[1:0] = 10

•

Capacitive load CL = 30 pF

•

Measurement points done at 0.5 × VDD level

•

I/O compensation cell activated

•

HSLV activated when VDD ≤ 2.7 V

•

Voltage scaling range 1

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics (SCK, SD, FS).

Table 148. SAI characteristics(1)

Symbol

Parameter

Conditions

Min Max Unit

fMCK

SAI main clock

output

MHz

fSCK

SAI clock

frequency(2)

Master transmitter, 2.7 V ≤ VDDIOX ≤ 3.6 V

Master transmitter, 1.71 V ≤ VDDIOX ≤ 3.6 V

Master receiver, 1.71 V ≤ VDDIOX ≤ 3.6 V

21.5

Slave transmitter, 2.7 V ≤ VDDIOX ≤ 3.6 V

27.5

Slave transmitter, 1.71 V ≤ VDDIOX ≤ 3.6 V

Slave receiver, 1.71 V ≤ VDDIOX ≤ 3.6 V

tv(FS)

FS valid time

Master mode, 2.7 V ≤ VDDIOX ≤ 3.6 V

Master mode 1.71 V ≤ VDDIOX ≤ 3.6 V

th(FS)

FS hold time

Master mode

tsu(FS)

FS setup time

Slave mode

2.5

th(FS)

FS hold time

Slave mode

tsu(SD_A_MR) Data input

setup time

Master receiver

tsu(SD_B_SR)

Slave receiver

th(SD_A_MR) Data input hold

time

Master receiver

th(SD_B_SR)

Slave receiver

tv(SD_B_ST)

Data output

valid time

Slave transmitter (after enable edge), 2.7 V ≤ VDDIOX ≤ 3.6 V

Slave transmitter (after enable edge), 1.71 V ≤ VDDIOX ≤ 3.6 V

27.5

th(SD_B_ST)

Data output

hold time

Slave transmitter (after enable edge)

tv(SD_A_MT)

Data output

valid time

Master transmitter (after enable edge), 2.7 V ≤ VDDIOX ≤ 3.6 V

Master transmitter (after enable edge), 1.71 V ≤ VDDIOX ≤ 3.6 V

27.5

th(SD_A_MT)

Data output

hold time

Master transmitter (after enable edge)

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