DIX4192IPFBT datasheet(32/60 Pages) BURR-BROWN

32 / 60 page

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SN74AHCT1G125

orEquivalent

+5V

Directtoexternallogic

operatingfromtheVIOsupply.

AESOUT

To+5VLogic

(VIOsupply=+3.0Vto+3.3V)

SN74AVC1T45

orEquivalent

IfVIO<+3.0V.

VIO

+5V

+3.3V

ToBalancedorUnbalanced

LineInterface

AESOUT

ToBalancedorUnbalanced

LineInterface

SN75ALS191

DIX4192

SBFS031C – JANUARY 2006 – REVISED JUNE 2006

APPLICATIONS INFORMATION (continued)

Figure 33. CMOS/TTL Output Logic Interface

Figure 34. External Line Driver Interface

The DIX4192 organizes the on-chip registers and data buffers into four pages. The currently active page is

chosen by programming the Page Selection Register to the desired page number. The Page Selection Register

is available on every register page at address 0x7F, allowing easy movement between pages. Table 2 indicates

the page selection corresponding to the Page Selection Register value.

Table 2. Register Page Selection

Page Selection Register Value (Hex)

Selected Register Page

Page 0, control and status registers

Page 1, DIR channel status and user data buffers

Page 2, DIT channel status and user data buffers

Page 3, reserved

DIX4192. In addition, status registers are provided for flag and error conditions, with many of the status bits

capable of generating an interrupt signal when enabled. See Table 3 for the control and status register map.

buffers correspond to the data contained in the C and U bits of the previously received block of the

AES3-encoded data stream. The contents of these buffers may be read through the SPI or I2C serial host

interface and processed as needed by the host system. See Table 5 for the DIR channel status buffer map, and

Table 6 for the DIR user data buffer map.

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