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DIX4192IPFBT Datasheet(PDF) 35 Page - Burr-Brown (TI) |
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DIX4192IPFBT Datasheet(HTML) 35 Page - Burr-Brown (TI) |
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35 / 60 page ![]() www.ti.com DIX4192 SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 01: Power-Down and Reset Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) RESET 0 PDALL PDPA PDPB PDTX PDRX 0 PDRX Power-Down for the Receiver Function Block This bit is utilized to power-down the DIR and associated functions. All receiver outputs are forced low. PDRX Receiver Power-Down Mode 0 Enabled (default) Disabled; the Receiver function block will operate normally based upon the applicable 1 control register settings. PDTX Power-Down for the Transmitter Function Block This bit is utilized to power-down the DIT and associated functions. All transmitter outputs are forced low. PDTX Transmitter Power-Down Mode 0 Enabled (default) Disabled; the Transmitter function block will operate normally based upon the applicable 1 control register settings. PDPB Power-Down for Serial Port B This bit is utilized to power-down the audio serial I/O Port B. All port outputs are forced low. PDPB Port B Power-Down Mode 0 Enabled (default) 1 Disabled; Port B will operate normally based upon the applicable control register settings. PDPA Power-Down for Serial Port A This bit is utilized to power-down the audio serial I/O Port A. All port outputs are forced low. PDPA Port A Power-Down Mode 0 Enabled (default) 1 Disabled; Port A will operate normally based upon the applicable control register settings. PDALL Power-Down for All Functions This bit is utilized to power-down all function blocks except the host interface port and the control and status registers. PDALL All Function Power-Down Mode 0 Enabled (default) Disabled; all function blocks will operate normally based upon the applicable control register 1 settings. RESET Software Reset This bit is used to force a reset initialization sequence, and is equivalent to forcing an external reset via the RST input (pin 24). RESET Reset Function 0 Disabled (default) 1 Enabled; all control registers will be reset to the default state. Register 02: Global Interrupt Status (Read-Only) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 TX RX 0 RX Receiver Function Block Interrupt Status (Active High) When set to 1, this bit indicates an active interrupt from the DIR function block. This bit is active high. The user should then read status registers 0x14 and 0x15 in order to determine which of the sources has generated an interrupt. TX Transmitter Function Block Interrupt Status (Active High) When set to 1, this bit indicates an active interrupt from the DIT function block. This bit is active high. The user should then read status register 0x0A in order to determine which of the sources has generated an interrupt. 35 Submit Documentation Feedback |
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