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DIX4192IPFBT Datasheet(PDF) 52 Page - Burr-Brown (TI) |
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DIX4192IPFBT Datasheet(HTML) 52 Page - Burr-Brown (TI) |
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52 / 60 page ![]() www.ti.com CHANNEL STATUS AND USER DATA BUFFER MAPS DIX4192 SBFS031C – JANUARY 2006 – REVISED JUNE 2006 Register 7F: Page Selection Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 0 0 0 0 0 0 PAGE1 PAGE0 PAGE[1:0] Page Selection These bits are utilized to select one of three register pages for write and/or read access via the SPI or I2C serial host interface. The Page Selection Register is present on every register page at address 0x7F, allowing movement between pages as necessary. PAGE1 PAGE0 Register/Buffer Page Selection 0 0 Page 0, control and status registers (default) 0 1 Page 1, DIR channel status and user data buffers 1 0 Page 2, DIT channel status and user data buffers 1 1 Page 3, reserved Table 5 through Table 8 show the buffer maps for the DIR and DIT channel status and user data buffers. For Table 5, the channel status byte definitions are dependent on the transmission mode, either Professional or Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode. This is applicable for Table 5 and Table 6. For Table 7, the channel status byte definitions are dependent on the transmission mode, either Professional or Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode. In Professional mode, Byte 23 for each channel is reserved for CRC data, which is automatically calculated and encoded by the DIT. There is no need to program Byte 23 for either channel in Professional mode. 52 Submit Documentation Feedback |
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