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SL2S3003FUD Datasheet(PDF) 17 Page - NXP Semiconductors

Part # SL2S3003FUD
Description  ICODE 3 (TagTamper)
PDF  82 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SL2S3003FUD Datasheet(HTML) 17 Page - NXP Semiconductors

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NXP Semiconductors
SL2S3003/SL2S3003TT
ICODE 3 (TagTamper)
Field
Bit
Values at
Delivery
Description
PPC_PTNR
8
0b
The Protection Pointer Address defines the base address for the password
protection of the higher user memory segment Page H. All block addresses
smaller than the protection pointer address are in the user memory segment Page
L. Section 8.5.3.6
Table 10. PPC_PNTR byte (Protect Page Pointer Address) configuration parameter descriptions
Bit number
0
1
2
3
4
5
6
7
RL
WL
RFU
RH
WH
RFU
Table 11. PPC_CTRL byte (Protect Page Control)
Field
Bit
Values at
Delivery
Description
RL
1
0b
Defines read password protection for Page L as defined with Section 8.5.3.6
WL
1
0b
Defines write password protection for Page L as defined with Section 8.5.3.6
RH
1
0b
Defines read password protection for Page H as defined with Section 8.5.3.6
WH
1
0b
Defines write password protection for Page H as defined with Section 8.5.3.6
Table 12. PPC_CTRL byte configuration parameter descriptions
Field
Bit
Values at
Delivery
Description
LP_PTNR
8
0b
The Lock Pointer Address defines the block from which the user memory
is divided into two pages (Page L and Page H) for the write lock (see in
Section 8.5.2.3). All block addresses smaller than the Lock Pointer Address are in
the user memory segment Page L. The lock conditions for those two pages L and
H are defined with the settings in the LP_CTR byte (see in Table 14).
Table 13. LP_PNTR byte (Lock Protection Pointer Address) configuration parameter descriptions
SL2S3003/SL2S3003TT
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 3.0 — 28 March 2024
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