M24M02E-F datasheet(11/54 Pages) STMICROELECTRONICS

Part #	M24M02E-F

Description	2-Mbit serial I²C bus EEPROM with configurable device address, software write protection registers, and preprogrammed device address

PDF	54 Pages

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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5.1

Start condition

The start condition is identified by a falling edge of serial data (SDA) while the serial clock (SCL) is stable in the

high state. This condition must precede any data transfer instruction. The device continuously monitors the SDA

and SCL for a start signal, except during a write cycle.

5.2

Stop condition

The stop condition is identified by a rising edge of serial data (SDA) while the serial clock (SCL) is stable in the

high state. This condition terminates the communication between the device and the bus controller. A read

instruction followed by NO ACK can be followed by a stop condition to force the device into the standby mode. A

stop condition at the end of a write instruction triggers the internal write cycle.

5.3

Data input

During data input, the device samples the serial data (SDA) on the rising edge of the serial clock (SCL). For

proper device operation, the SDA must be stable during the rising edge of the SCL, and the SDA signal must

change only when the SCL is driven low.

5.4

Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether a bus controller

or target device, releases serial data (SDA) after sending eight bits of data. During the ninth clock pulse period,

the receiver pulls SDA low to acknowledge the receipt of the eight data bits.

M24M02E-F

Device operation

DS14157 - Rev 2

page 11/54

M24M02E-F Datasheet(PDF) 11 Page - STMicroelectronics