M24M02E-F datasheet(27/54 Pages) STMICROELECTRONICS

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6.5.2

Read operation on CDA register

Following a start condition the bus controller sends a device select code with the R/W bit (RW) set to 0. The

device acknowledges this and waits for the address bytes where the CDA register is located. The device

responds to each address byte with an acknowledge bit. Then, the bus controller sends another start condition,

and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the

contents of the CDA register. See in Table 9, Table 10, and Table 11 how to address the configurable device

address register.

After the successful completion of a read configurable device address, the device internal address counter is not

incremented by one, to point to the next byte address. Reading more than one byte with the sequential random

read command loops on reading the configurable device address register value.

To terminate the stream of data byte, the bus controller must not acknowledge the byte, and must generate a stop

condition, as shown in Figure 19. Random read CDA register.

The configurable device address register cannot be read while a write cycle (tW) is ongoing.

The configurable device address bit (C2) value can be checked by sending the device select code.

•

If the chip enable address b3 sent in the device select code is matching with the C2 value, the device

sends an ACK.

•

Otherwise, the device answers no ACK.

Figure 19. Random read CDA register

Dev sel*

Byte addr

Data out

ACK

NO ACK

ACK

Dev sel*

*: The seven most significant bits of the first device select code in a random read must match those of the device

select code in the write operation.

6.5.3

Read operation on SWP register

Following a start condition the bus controller sends a device select code with the R/W bit (RW) set to 0. The

device acknowledges this and waits for the address bytes where the SWP register is located. The device

responds to each address byte with an acknowledge bit. Then, the bus controller sends another start condition,

and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the

contents of the SWP register. See in Table 9, Table 10, and Table 11 how to address the software write protection

After the successful completion of a read operation on SWP, the device internal address counter is not

incremented by one, to point to the next byte address. Reading more than one-byte with the sequential random

read command loops on reading the SWP register value.

To terminate the stream of data byte, the bus controller must not acknowledge the byte, and must generate a stop

condition, as shown in Figure 20.

The SWP register cannot be read while a write cycle (tW) is ongoing.

Figure 20. Random read SWP register

Dev sel*

Byte addr

Data out

ACK

NO ACK

ACK

Dev sel*

*: The seven most significant bits of the first device select code in a random read must match those of the device

select code in the write operation.

M24M02E-F

Instructions

DS14157 - Rev 2

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