M24M02E-F datasheet(26/54 Pages) STMICROELECTRONICS

26 / 54 page

6.5

Read operations on features

Only the random address read or sequential random read commands are authorized to access the four additional

features. The address counter contains meaningful address value only after these authorized commands have

been performed.

6.5.1

Read operation on DTI register

Following a start condition the bus controller sends a device select code with the R/W bit (RW) set to 0. The

device acknowledges this and waits for the address bytes where the DTI register is located. The device responds

to each address byte with an acknowledge bit. Then, the bus controller sends another start condition, and repeats

the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the

DTI register. See in Table 9, Table 10, and Table 11 how to address the device type identifier register.

After the successful completion of a read device type identifier, the device internal address counter is not

incremented by one, to point to the next byte address. Reading more than one byte with the sequential random

read command loops on reading the device type identifier register value.

To terminate the stream of data byte, the bus controller must not acknowledge the byte, and must generate a stop

condition, as shown in Figure 18.

The device type identifier register cannot be read while a write cycle (tW) is ongoing.

Figure 18. Random read DTI register

Dev sel*

Byte addr

Data out

ACK

NO ACK

ACK

Dev sel*

*: The seven most significant bits of the first device select code in a random read must match those of the device

select code in the write operation.

M24M02E-F

Instructions

DS14157 - Rev 2

page 26/54

M24M02E-F Datasheet(PDF) 26 Page - STMicroelectronics