M24M02E-F datasheet(19/54 Pages) STMICROELECTRONICS

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6.2.4

Write operation on identification page

Write operations on the identification page are performed according to the state of the WC line or to the lock/

unlock status. Following a start condition the bus controller sends a device select code with the R/W bit (RW) set

to 0. The device acknowledges this, as shown in Figure 12, and waits for the address bytes where the

identification page is located. The device responds to each address byte with an acknowledge bit, and then waits

for the data byte. See in Table 9, Table 10 and Table 11 how to address the identification page.

When the bus controller generates a stop condition immediately after the data byte ACK bit (in the tenth bit time

slot), the internal write cycle tW is triggered. The device internal address counter is automatically incremented to

point to the next byte after the last modified byte.

A stop condition at any other time slot does not trigger the internal write cycle.

During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any

requests (NO ACK).

If the identification page is already locked in read-only mode (lock status) or hard write protected with WC line

driven high, the write operation on the identification page is not executed and the accompanying data bytes are

not acknowledged as shown in Figure 13. Write identification page (page locked or hard protected).

Figure 12. Write identification page (page unlocked)

Byte Write

Dev sel

Byte addr

Data in

Page Write

Dev sel

Byte addr

Data in 1

Page Write

(cont'd)

Data in N

R/W

ACK

R/W

ACK

M24M02E-F

Instructions

DS14157 - Rev 2

page 19/54

M24M02E-F Datasheet(PDF) 19 Page - STMicroelectronics