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M65KG512AB8W9 Datasheet(PDF) 30 Page - STMicroelectronics

Part # M65KG512AB8W9
Description  512Mbit (4 banks x 8 Mb x 16) 1.8 V supply, DDR low power SDRAM
PDF  54 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M65KG512AB8W9 Datasheet(HTML) 30 Page - STMicroelectronics

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DC and ac parameters
M65KG526AB
30/54
tRP
RAS Precharge time
22.5
ns
tREF
Average Periodic Refresh time
7.8
µs
tSRE
tSREX
Self Refresh Exit Time
165
ns
tWPRES
Write Preamble setup time
0
ns
1.
The above timings are measured according to the test conditions shown in Table 10: Operating and ac measurement
conditions with driver strength set to “Full Strength” (EMR5 to EMR6 = ‘00’).
2.
These timings define the signal transition delays from K or K cross point, that is when K or K signal crosses VREF.
3.
The timing reference level is VREF.
4.
tOHZ and tDQSHZ define the transition time from Low-Z to High-Z of DQ0-DQ15 and UDQS/LDQS, at the end of a Burst
Read operation, respectively. They specify when data outputs stop being driven.
5.
tOLZ and tDQSLZ define the transition time from High-Z to Low-Z of DQ0-DQ15 and UDQS/LDQS, at the end of a Burst Read
operation. They specify when data outputs begin to be driven.
Table 15.
AC characteristics(1) - TJ = −30 to 85 °C (continued)
Symbol
Alt
Parameter
M65KG512AB
Unit
Min
Max
Table 16.
AC characteristics(1) - TJ = −30 to 105 °C
Symbol
Alt
Parameter
M65KG512AB
Unit
133MHz
166MHz
Min
Max
Min
Max
tAC
(2)
Data Output access time from K and K
1.5
6.0
2.0
5.0
ns
tAS
(3)
tIS
Address and Control Input setup time
1.4
1.4
ns
tAH
(3)
tIH
Address Control Input hold time
1.4
1.4
ns
tCK
Clock Cycle Time
7.5
6.0
ns
tDQSCK
(2)
UDQS/LDQS access time from K and K
1.5
6.0
2.0
5.0
ns
tDIPW
Data Output and LDQM/UDQM inputs pulse width
1.8
1.75
ns
tDQSHZ
(4)
UDQS/LDQS High-Z Time from K and K
1.5
6.0
1.5
4.5
ns
tDQSLZ
(6)
UDQS/LDQS Low-Z time from K and K
1.5
6.0
1.5
4.5
ns
tDQSQ
(3)
UDQS/LDQS to Data Output skew
0.65
0.5
ns
tDS
(3)
Data Input and UDQM/LDQM setup time
0.9
0.9
ns
tDH
(3)
Data Input and UDQM/LDQM hold time
0.9
0.9
ns
tDAL
Data Input Valid to Precharge command
2tCK+22.5
tWR+tRP
ns
tIPW
Addresses and control pulse width
2.8
2.7
ns
tOHZ
(4)
tHZ
Data Output High-Z from K and K
1.5
6.0
1.0
5.5
ns
tOLZ
(5)
tLZ
Data Output Low-Z from K and K
1.5
6.0
1.0
5.5
ns
tQH
Data and LDQS/UDQS Output hold time from
DQS
tHP-tQHS
tHP-tQHS
ns
tQHS
Data hold skew factor
0.75
0.65
ns
tRAS
RAS Active Time (Bank (Row) Activate to Bank
Precharge)
60
120000
54
120000
ns



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