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M65KG512AB8W9 Datasheet(PDF) 45 Page - STMicroelectronics

Part # M65KG512AB8W9
Description  512Mbit (4 banks x 8 Mb x 16) 1.8 V supply, DDR low power SDRAM
PDF  54 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M65KG512AB8W9 Datasheet(HTML) 45 Page - STMicroelectronics

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M65KG526AB
DC and ac parameters
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Figure 24.
Write followed by Read (Write completed)
1.
If the Read operation is performed to the same bank and row than the Write operation, the READ command should be
performed tWRD after the WRIT command to complete the Write operation.
2.
If the Read operation is performed to the same bank but to a different row, the bank must be precharged tWPD after the
Write operation. tRP after the Precharge command, issue the ACT command. The READ command can then be issued
tRCD after the ACT command.
3.
If the Read operation is performed to a different bank and to an active row, the sequence is identical to the one described in
Note 1
4.
If the Read operation is performed to a different bank and to an idle row, the bank must be precharged independently from
the Write operation. tRP after the Precharge command, issue the ACT command. The WRIT command can then be issued
tRCD after the ACT command.
Command
K
K
DI1
UDQS,
LDQS
DQ0-DQ15
WRIT
NOP
t0
t1
t2
t3
t4
t5
tWRDmin (3)
DI0
ai10838b
t6
t7
t8
READ
NOP
Note: 1. Burst Length = 4
2. CAS Latency = 3 (CL)
3. tWRD = BL/2 + 2 clock cycles
UDQM,
LDQM
DO0 DO1 DO2
Data Input
Data Output
DI2 DI3
DO3



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