PPC440EPX-SPAFFFTS datasheet(11/94 Pages) AMCC

11 / 94 page

440EPx – PPC440EPx Embedded Processor

Revision 1.26 – October 15, 2007

AMCC Proprietary

Preliminary Data Sheet

PowerPC 440 Processor

The PowerPC 440 processor is designed for high-end applications: RAID controllers, SAN, iSCSI, routers,

switches, printers, set-top boxes, etc. It implements the Book E PowerPC embedded architecture and uses the

128-bit version of IBM’s on-chip CoreConnect Bus Architecture.

Features include:

• Up to 667MHz operation

• PowerPC Book E architecture

•32KB I-cache, 32KB D-cache

– UTLB Word Wide parity on data and tag address parity with exception force

• Three logical regions in D-cache: locked, transient, normal

• D-cache full line flush capability

• 41-bit virtual address, 36-bit (64GB) physical address

• Superscalar, out-of-order execution

• 7-stage pipeline

• 3 execution pipelines

• Dynamic branch prediction

• Memory management unit

– 64-entry, full associative, unified TLB with optional parity

– Separate instruction and data micro-TLBs

– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian

• Debug facilities

– Multiple instruction and data range breakpoints

– Data value compare

– Single step, branch, and trap events

– Non-invasive real-time trace interface

• 24 DSP instructions

– Single cycle multiply and multiply-accumulate

– 32 x 32 integer multiply

– 16 x 16 -> 32-bit MAC

Floating Point Unit (FPU)

The chip has a built-in super scalar FPU that supports both single- and double-precision operations, and offers

single cycle through put on most instructions.

Features include:

• Five stages with 2 MFlops/Hz

• Hardware support for IEEE 754

• Single- and double-precision

• Single-cycle throughput on most instructions

• Thirty-two 64-bit floating point registers

SRAM Controller

The internal SRAM controller (ISC) supports the following features:

• One bank (Bank 0) of 16 KB configurable as 4KB, 8KB or 16KB (128 bits wide)

• 128-bit slave attachment addressable by any PLB master

• Transfers by PLB slave cycles:

– Single-beat read and write (1 to 8 bytes for 64-bit masters, 1 to 16 bytes for 128-bit masters)

– 4-word line read and write

– 8-word line read and write

– Double word read and write bursts for 64-bit masters

– Quadword read and write bursts for 128-bit masters

PPC440EPX-SPAFFFTS Datasheet(PDF) 11 Page - Applied Micro Circuits Corporation

PPC440EPX-SPAFFFTS Datasheet(HTML) 11 Page - Applied Micro Circuits Corporation

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