PPC440EPX-SPAFFFTS datasheet(73/94 Pages) AMCC

73 / 94 page

440EPx – PPC440EPx Embedded Processor

Revision 1.26 – October 15, 2007

AMCC Proprietary

Preliminary Data Sheet

Thermal Monitor

Thermal monitoring of the chip is accomplished using the PNP transistor (

β ≈ 2) provided on the chip. The collector

of the transistor is connected to ground (GND). The emitter (TherMonA) and base (TherMonB) are connected to

chip pins. A voltage measurement (VBE1 and VBE2) across the TherMonA and TherMonB pins at the two current

values I1 and I2 provides the chip temperature in °K according to the equation:

T = (q/nk)(VBE2−VBE1)/ln(I2/I1) °K where q = 1.602 176 53×10

-19, n = 1.0 ± 0.015, and k = 1.380 6505×10-23.

Note: VBE2 and VBE1 should be specified in Volts. I1 and I2 can be any units of measure provided they are the

same. The small values require precision measurement and current sources.

The calculated on chip (ball to ball) series resistance for the PPC440EPx thermal monitor circuit is 2.0 ohms. The

thermal sensor reflects the PPC440EPx junction temperature.

TherMonA

TherMonB

PPC440EPx

I1, I2 (Max = 300μA)

VBE1, VBE2

Note: The bias voltage VEB should be between +0.5V and +0.7V.

Test Conditions

Output

50pF

Clock timing and switching characteristics are specified in accordance with operating

conditions shown in Table 10 on page 66. AC specifications are characterized with

VDD = +1.5V, TC = +85 °C and a 50pF test load as shown in the figure to the right.

Table 18. Clocking Specifications

Symbol

Parameter

Min

Max

Units

Notes

SysClk Input

Frequency

33.33

66.66

MHz

Period

TCS

Edge stability (cycle-to-

cycle jitter)

–

±0.15

TCH

High time

40% of nominal

period

60% of nominal

period

TCL

Low time

40% of nominal

period

60% of nominal

period

Note: Input slew rate

≥ 1V/ns

PLL VCO

Frequency

600

1333.33

MHz

Period

0.750

1.66

Processor (CPU) Clock

Frequency

333.33

666.66

MHz

PPC440EPX-SPAFFFTS Datasheet(PDF) 73 Page - Applied Micro Circuits Corporation

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