PPC440EPX-SPAFFFTS datasheet(69/94 Pages) AMCC

69 / 94 page

Receiver

AC Overshoot (V)

DC Overshoot (V)

DC Undershoot (V)

AC Undershoot (V)

TOS

3.3V LVTTL

3.9

3.6

-0.16

-0.6

0.1*TCYC

2.5V (3.3V tolerant)

3.9

3.6

-0.16

-0.6

0.1*TCYC

DDR

1.2*SOVDD

SOVDD + 0.3

-0.3

-0.6

0.1/MemClkOut

PCI

1.2*OVDD

OVDD + 0.5

-0.5

-0.2*OVDD

0.1/PCIClk

Notes:

1. TCYC is the period of the bus clock.

1/PerClk - EBC and NAND flash interfaces.

1/GMCRXClk - GMII and MII modes

1/SMIIRefClk - SMII mode

1/GMCGRXClk - RGMII mode

1/USB2Clk - UTMI

1/TrcClk - instruction trace interface

1/IIC0Clk and 1/IIC1Clk - IIC interfaces

1/SPIClkOut - SPI

440EPx – PPC440EPx Embedded Processor

Revision 1.26 – October 15, 2007

AMCC Proprietary

Preliminary Data Sheet

Power Sequencing

Startup sequencing of the power supply voltages is not required. However, a power-down cycle must complete

(OVDD and VDD are below +0.4V) before a new power-up cycle is started.

Analog Voltage Filter

The analog voltages (AVdd, EAVdd, and UnAVdd) used for the on-chip PLLs can be derived from the logic voltage, but must be

filtered before the PPC440EPx. A Separate filter, as shown below, is recommended for each voltage.

• The filter should keep the analog voltage to analog ground compression/expansion due to noise less than +50

mV.

• Keep all wire lengths as short as possible.

• Analog grounds must be brought out and connected to the digital ground plane at the filter capacitor.

• The impedance of the ferrite bead should be much greater than that of the capacitor at frequencies where

noise is expected.

VDD

L – SMT ferrite bead chip, Murata

BLM21PG600SN1

GND

AVDD, SAVDD, UnAVdd

AGND, SAGND, UnAGND

Table 12. Overshoot and Undershoot

PPC440EPX-SPAFFFTS Datasheet(PDF) 69 Page - Applied Micro Circuits Corporation

PPC440EPX-SPAFFFTS Datasheet(HTML) 69 Page - Applied Micro Circuits Corporation

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