PPC440EPX-SPAFFFTS datasheet(86/94 Pages) AMCC

86 / 94 page

440EPx – PPC440EPx Embedded Processor

Preliminary Data Sheet

AMCC Proprietary

Revision 1.26 – October 15, 2007

insertion buffer.

When using unbuffered DIMMS, the loading on the address bus will be considerably greater than the clock (up to

18 loads for double-sided DIMMs). In this case, it is strongly suggested that a delay of 500ps in the clock path so

that the Address/Command setup time at the DIMMs can be met. This delay is sufficient to meet the setup time,

without having to change the programmable delay (internal to the PPC440EPx) between the DQS/DQ/DM and the

clock (assuming nominal settings as specified in the PPC440EPx Users Manual). While the clock is now 500ps

later than the nominal DQS arrival time, this still falls well within the window allowed by the JEDEC spec for TDQSS

(± 0.25 cycle, or 1.5ns at 166MHz). In the case where it is not possible to anticipate which kind of DIMMs may be

employed in a system, it is always safe to use this 500ps clock delay, since registered DIMMs (the least heavily

loaded) will have more than enough margin (almost 1/2 cycle) to accommodate the slight decrease in address hold

time.

Termination Model

Figure 10. DDR SDRAM Simulation Signal Termination Model

10pF

MemClkOut

120

30pF

Addr/Ctrl/Data/DQS/DM (DDR1)

VTT = SOVDD/2

PPC440EPx

Addr/Ctrl (DDR2)

Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.

It is not a recommended physical circuit design for this interface. An actual interface design will depend on many

factors, including the type of memory used and the board layout.

DDR2 SDRAM On-Die Termination Impedance Setting

For all DDR2 applications, the On-Die Termination (ODT) impedance value must be set to 75 ohms in the DIMM

Extended Mode Register (EMR) in order to optimize the data transmission during memory write operations.

PPC440EPX-SPAFFFTS Datasheet(PDF) 86 Page - Applied Micro Circuits Corporation